Reset Configuration Information
The following table describes the reset configuration information that
is displayed at reset.
Table 5. Reset Configuration
Signal at Reset
Configuration (asserted/deasserted)
FLUSH#
Output Tristate Enabled/Disabled
INIT#
Built-in Self Test Enabled/Disabled
A8#
AERR# Observation Policy Enabled/Disabled
A9#
BERR# Observation Policy Enabled/Disabled
A10#
BINIT# Observation Policy Enabled/Disabled
A7#
In-order Queue depth = 1/8
A6#
Power-on Reset Vector = 000FFFF0 or FFFFFFF0 hex
A5#
FRC Mode Enabled/Disabled
A[12:11]#
APIC Cluster ID (00, 01, 10, 11)
Reset Configuration
Figure 19
2-20
Preprocessor Interface for the Pentium II Processor
Содержание E2466C
Страница 10: ...1 Setting Up the Preprocessor Interface ...
Страница 31: ...1 22 Preprocessor Interface for the Pentium II Processor ...
Страница 32: ...2 Analyzing the Pentium II Processor ...
Страница 53: ...2 22 Preprocessor Interface for the Pentium II Processor ...
Страница 54: ...3 Preprocessor Interface Hardware Reference ...
Страница 77: ...3 24 Preprocessor Interface for the Pentium II Processor ...
Страница 78: ...A If You Have a Problem ...