HP 9000 rp3410, Руководство пользователя и обслуживания

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Chapter 1
Overview
Detailed Server Description
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• IDE controller
• USB controller
• 10/100/1000 LAN
PA RISC Processor
The system board consists of two Zero Insertion Force (ZIF) processor sockets, the Core Electronic Complex
(CEC), and circuits for clock and power generation and distribution, boundary Scan, In-target Probe (ITP),
and debug.
The Front Side Bus (FSB) is the IA64 processor bus based on bus protocol from Intel. This enables processor
customer self-repair (CSR) parts to be dropped in, provided that electrical and mechanical compatibility and
support circuitry exist. A processor CSR consists of a dual processor module with heatsink assembly.
One end of the FSB is terminated with an I/O ASIC. The other end of the bus is terminated with a CSR. An
additional CSR can be loaded in the middle. For the system to function properly, the processor farthest away
from the I/O ASIC must be loaded at all times to electrically terminate the FSB.
Each processor module plugs directly into and is powered by its own 12V to 1.2V power-pod. Other power for
the system board comes from multiple on-board dc/dc converters. Each processor module is attached to the
board through a ZIF socket and the entire CSR secured down by a heatsink bolster plate.
Processor Bus
The processor bus (Front Side Bus [FSB]) in this product runs at 200 MHz. Data on the FSB are transferred
at a double data rate, which enables a peak FSB bandwidth of 6.4 Gb/sec.
ZX1 I/O and Memory Controller
HP 9000 rp3410 and rp3440 servers support the following features of the ZX1 I/O and memory controller
chip:
• 3.3 GB/s peak IO bandwidth.
• Provides eight communication paths.
• Peak memory bandwidth of 8.5 GBs.
• Two memory cells, 144 data bits each.
Memory
The memory subsystem provides two memory cells, each of which is 144 data bits wide. Each cell has six
DIMM slots, which means a total of 12 DIMM slots are available. The memory bus clock speed is 133 MHz,
and the data transfer rate is 266Mtransfers/second as data is clocked on both edges of the clock. The peak
data bandwidth for this memory subsystem design is 8.5 GB/s. DIMMs must be loaded in quads with
qualified modules, with the exception of 256 MB DIMMs which is loaded in pairs. Memory is protected by
data error correction code (ECC), and the hardware implementation supports the chip-spare feature.
The minimum amount of memory that you can install is 512 MB (2x256 MB modules in a HP 9000 rp3410
model A7136A server), and 1 GB (4x256 MB modules in other HP 9000 rp34x0 servers). The maximum
amount of memory that you can install is limited to 24 GB (12 x 2 GB modules) or 32 GB (8 x 4 GB modules)
in a HP 9000 rp3440 server.
This design does not support any non industry-standard DDR DIMMs. Only qualified DIMMs are supported.