Interface, Circuit Description
Interface provides data transfer between Al5 Controller and A3 Digital Storage. This
assembly also includes qualifier selection for
branching, input/output (I/O) port
decoding, and the main clock circuits.
Data Transfer Register
U2, U7, U8, and form a 16-bit Data Transfer Register which can be loaded or output onto
either the Instrument Bus (through
and
the Instrument Bus Drivers) or the Digital
Storage Bus (through U3, U4, and U5, the Digital Storage Bus Drivers).
Instrument Address Decoder
U6, U14, and U15 control the loading and output of data between the Data Transfer Register
and the Instrument Bus.
Qualifier Select
and U21 select one of 16 qualifiers to be used for conditional branching. Selection is
controlled by
Main Control firmware.
I/O Port Decoder
U18 and
decode I/O port control signals from the Pipeline Registers in
Main
Control.
Timing Generator
U12, and U13 generate 8 MHz, 1 MHz, and 200
timing signals used by A3
Digital Storage.
1
Содержание 85662A
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Страница 409: ...Table 4 Video Bandwidth Truth Table 6 A4A9 ...
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Страница 452: ...A4A6A2 Output Driver Component Locations 85662 60170 Option 067 Tab ...
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Страница 473: ...Table 4 Video Bandwidth Truth Table Option H96 3 ...
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Страница 594: ...HEWLETT PACKARD HP Part No 85662 90085 Printed in USA ...