HP 85662A, Руководство по устранению неисправностей и ремонту

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Blink
The output of U12 is a 1 Hz signal with a 90 percent duty cycle. When enabled by the
BLINK command stored in the Input Register, this signal causes display blinking.
Long Line/Short Line Timing
This circuit receives signal LGCLK from Interface and signal LL from the Input
Register. It generates signal INTR, which is a string of 1 pulses. When LL is low the
pulses are spaced 5 apart; when LL is high the pulses are 20 apart. This provides the
timing signals for the 4 and 19 Line Generator drawing periods and 1 setup period.
Integrator Switch Driver
This circuit provides the drive signals for the Integrator switches in Line Generator.
Q13 and Q14 form a complementary driver. When the input is low, Q13 is on and Q14 is off,
setting INTG to -5 V and LINTG to 4.7 V nominal. When the input is high, Q13 is off and
14 is on, setting INTG to V nominal and LINTG to -5 V.
Sample and Hold Switch Driver
This circuit provides the drive signals for the Sample and Hold circuits of the Line Generator
X, Y, and Z axes. and Q12 form a complementary driver. A -9.6 V reference is provided
by and associated circuitry. is a level translator. When pin 11 goes low,
collector goes to -10.3 V, turning off and Q12 on. Signals HLDX and HLDY go to 0 V,
and signal SMPL goes to -7.6 V nominal. When pin 11 goes high, collector goes to
-8.9 V, turning on and Q12 off. SMPL goes to 0 V and collector goes to -8.4 V
nominal. Potentiometers R50 (X S&H BAL) and R51 (Y S&H BAL) are used to adjust the
HLDX and HLDY drive levels to
Line Generator. Cl8 and Q5 speed the rise time of
the HLDX and HLDY signals. As pin 11 goes from high to low, the base of goes low,
causing Q5 to turn on and the HLDX and HLDY signals to rise almost instantaneously.
Blanking Logic
This circuit provides all display blanking. It muliplexes the retrace blanking of the fast scan
display (direct video and fast sweep) with the digital storage blanking. For the digital storage
display it provides blanking or unblanking as specified by signals LLGBLANK, BLINK,
and INTR. R30, R27, C16, R28, R32, and Cl5 are delay circuits which match the
delay of the LBLANK signal to the delay of the Line Generator. R31, R29, and Cl4 match
the retrace blanking delay to the fast sweep delay.
AUX Z
The AUX Z circuit receives the LBLANK signal from the Blanking Logic and the Z signal
from the Digital Storage/Fast Scan M
UX
. It generates the AUX BLANK and AUX Z signals.
R65 and R62 convert the 0 to 2 V range of Z to the 0 to 1 V range necessary for variation of
AUX Z intensity. U8 is a voltage follower with providing a high current output.
Blanking causes the AUX Z signal to drop to -1 V or less. When AUX BLANK goes high,
Q7 turns off and
turns on, causing AUX Z to go negative. When AUX BLANK IS LOW,
Q7 is on and is off.
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