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Refer to function block J of the Al6 fast ADC assembly schematic diagram in the
HP 8560 E-Series Spectrum Analyzer Component Level Information.
Peak detection or pit (negative peak) detection can be enabled whenever the sample rate is
less than 12 MHz (sweep times greater than 50
Peak detection uses the maximum value
of all the samples taken within each bucket (between adjacent display points). Pit detection
uses the minimum value of all the samples taken within each bucket. And sample detection
uses the last sample of all the samples taken within each bucket.
The different detection modes are implemented by selectively clocking latch
depending
on the state of
which is generated in PAL
(block A). When
is low,
is clocked by WCLK. When
is high,
is not clocked.
is a function of the
SCLK-1, LSAMPLE, LPEAK, P-LO, and P-HI signals. See Table 8-12.
If the sample rate is 12 MHz,
is high, which forces
low so that every sample
is clocked into latch
and latched into RAM U32 (block K). If the sample rate is less than
12 MHz and the detection mode is peak or pit, the SCLK-1, LPEAK, P-LO, and P-HI signals
control the
signal. In these detection modes, latch
stores the peak or pit value of
the samples taken for each bucket. The 8-bit digital magnitude comparator, U31, compares
the input byte (P) with the output byte (Q) from latch
When P is greater than Q,
P-LO is low (0) and P-HI is high (1). When P is less than Q, P-LO is high (1) and P-HI is
low (0). When P is equal to Q, P-LO and P-HI are both low (0). See Table 8-12.
Table 8-12.
Truth Table
I
Mode
I
I
I SCLK-1
I
LSAMPLE
I
LPEAK
I
P-LO
I
P-HI
I
L
H
X
X
X
x x
S A M P L E L
X
X
L
X
x x
PEAK
NEG
PEAK
(Pit)
Clocking
Peak/Pit
Sample
L
H
H
H
L
H
L
L
L
L
L
H
L
L
H
L
L
X
Refer to function block K of the Al6 fast ADC assembly schematic diagram in the
HP 8560 E-Series Spectrum
Analyzer
Component Level Information.
The static RAM stores the flash ADC samples that are taken when the fast ADC circuitry is
in the “write” mode. When not in the “write” mode, the static RAM is read by the CPU on
the A2 controller assembly to retrieve the fast ADC data.
The 8-bit Q bus connects the outputs of latch
to the data port of static RAM U32.
Section 8-33
Содержание 8562E
Страница 21: ...A l HP 85623 Interconnect Block Diagram A 5 Contents 14 ...
Страница 158: ...A9 Input Attenuator 9 c 9 d 1 slll3e Figure 4 15 A9 Mounting Screw at Right Side Frame Assembly Replacement 4 33 ...
Страница 172: ...Procedure 13 Rear Frame Rear Dress Panel Figure 4 23 A6 Power Supply Cover SP14E Assembly Replacement 4 47 ...
Страница 204: ...I _I 8560E Series I I sl134e F i g u r e 5 2 P a r t s I d e n t i f i c a t i o n C o v e r A s s e m b l y I I ...
Страница 205: ...8560E Series sl131e FIGURE 5 3 PARTS IDENTIFICATION MAIN CHASSIS v ...
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Страница 213: ...w51 W2 W52 N5A A4 _ w 5 5 w27 Figure 6 3 Top View A2 and A3 Unfolded S K 1 5 7 Major Assembly and Cable Locations 6 5 ...
Страница 217: ...w20 C O A X 6 w 7 w 5 9 C O A X a 3 9 sj138e Figure 6 7 Al6 Fast ADC Option 007 Major Assembly and Cable Locations 6 9 ...
Страница 219: ...FL 4 Bl Figure 6 9 Rear View BTl A20 SK162 Major Assembly and Cable Locations 6 l1 ...
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