HP 600 Series, Услуги и приложения

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Data Link Accelerator Architecture
Figure 4. Block Diagram of Data Link Accelerator
CPU The Data Link Accelerators (interface cards) for the HP Router
650 use the 33-megahertz Intel i960 CF RISC processor.
Data RAM Program variables and data critical to packet throughput
(such as routing and bridging tables) are stored in a fast memory.
Packet RAM Each DLA coprocessor stores packets received from the
line (the network medium) into packet RAM, and transmits packets
from packet RAM to the line.
Station ID PROM This stores the station (MAC) address for each of
the router’s ports.
LAN and WAN Controller Coprocessors National’s SONIC
(Systems-Oriented Network Interface Controller) is a second-generation
Ethernet controller that integrates a fully compatible 802.3
encoder/decoder. The token ring coprocessor is Texas Instruments’
TMS380C16/04 or TMS380C25. They support the 4-Mbit/s and 16-Mbit/s
data rates as well as universal and local ring addressing. A Motorola
FDDI chip set is used for the dual-attached stations on FDDI ports. The
MK5025 by SGS Thompson is the WAN coprocessor for serial frame
formatting, such as frame delimiting with flags and FCS (frame check
sequence) generation and detection. Other information about LAN and
WAN ports is found in the “Features of HP Routers” product note in this
book, and in the installation guides for your hardware.
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Architecture and Technology
Router 650 Hardware
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