
HP5501B
Service
8-32
8-91. A3
CONTROLLER/REFERENCE
BOARD AND A4 SAMPLER BOARD CIRCUIT
THEORY
8-92. Introduction
8-93. Figure 8-18 (two sheets) shows the schematic diagram for the A3 Controller/Reference Board
and the A4 Sampler Board.
8-94. The A1, A3, and A4 boards contain the electronics for the following portions of the Laser Head
Block Diagram:
•
Power Amplifier
•
Warmup Error Amplifier
•
Photodiode and Amplifier
•
Liquid Crystal
•
Clock and State Machine
•
Subtracting Sample and Hold
•
Reference Receiver
8-95. Clock
Ⓐ
8-96. The frequency of oscillator U10 is determined by timing components R8, C3, C7, and C8. For
normal operation, C7 gives an output frequency of approximately 100 Hz. For testing purposes
capacitors C3, C7, and C8 can be configured so that the oscillator circuit generates a 1000 Hz
output (JMP8 in HI
position). To troubleshoot using signature analysis, the oscillator can be
configured to run at 75 kHz (±20%) by removing the CLK FREQ jumper JMP8 completely.
8-97. Dividers
Ⓑ
8-98. The dividers, consisting of U4A and U6, convert the 100 Hz oscillator signal into the desired
periods. The first stage of the divider is U6, a dual 4-bit counter, which divides the 100 Hz by 256.
The last output of U6 at Pin 8 has a period of 2.56 seconds (nominal). The output of U4A at Pin
13 has a period of 5.12 seconds while the output at Pin 9 provides a period of 25.6 seconds.
These two outputs are AND’ed by U2C to produce a signal called DISABLE which is high 2.56
seconds out of every 25.6 seconds. DISABLE is used by the subtracting sample and hold circuit
and the power amplifier.
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