For all devices, the PWM clock source is the system clock f
SYS
.
Device
Channels
PWM Mode
Output Pin
PWM Register Name
HT46R47/HT46C47
1
6+2
PD0
PWM
HT46R22/HT46C22
1
6+2 or 7+1
PD0
PWM
HT46R23/HT46C23
(24-pin package)
1
6+2 or 7+1
PD0
PWM0
HT46R23/HT46C23
(28-pin package)
2
6+2 or 7+1
PD0/PD1
PWM0/PWM1
HT46R24/HT46C24
(28-pin package)
2
6+2 or 7+1
PD0/PD1
PWM0/PWM1
HT46R24/HT46C24
(48-pin package)
4
6+2 or 7+1
PD0/PD1/PD2/PD3
PWM0/PWM1/
PWM2/PWM3
PWM Function Table
This method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enables the
generation of higher PWM frequencies, which allow a wider range of applications to be served. As
long as the periods of the generated PWM pulses are less than the time constants of the load, the
PWM output will be suitable as such long time constant loads will average out the pulses of the
PWM output. The difference between what is known as the PWM cycle frequency and the PWM
modulation frequency should be understood. As the PWM clock is the system clock, f
SYS
, and as
the PWM value is 8-bits wide, the overall PWM cycle frequency is f
SYS
/256. However, when in the
7+1 mode of operation the PWM modulation frequency will be f
SYS
/128, while the PWM modula-
tion frequency for the 6+2 mode of operation will be f
SYS
/64.
PWM Modulation Frequency
PWM Cycle Frequency
PWM Cycle Duty
f
SYS
/64 for (6+2) bits mode
f
SYS
/128 for (7+1) bits mode
f
SYS
/256
[PWM]/256
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However,
in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as
modulation cycle 0 ~ modulation cycle 3, denoted as
²
i
²
in the table. Each one of these four
sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of
four is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the
PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted
here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In
the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the
following table.
Parameter
AC (0~3)
DC (Duty Cycle)
Modulation cycle i
(i=0~3)
i<AC
DC 1
64
+
i
³
AC
DC
64
6+2 Mode Modulation Cycle Values
Chapter 1 Hardware Structure
43
Содержание HT46R22
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