Holtek HT46R22, Руководство пользователя

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The HT46R24/HT46C24 devices have two internal timers, TMR0 and TMR1, and therefore re-
quire an additional timer control register TMR1C.
Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed time intervals, providing an internal inter-
rupt signal each time the counter overflows. To operate in this mode, the bit pair, TM1/TM0,
T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 1 and 0 respec-
tively. In this mode the internal clock is used as the timer clock. With the exception of TMR1 in the
HT46R24/HT46C24, the input clock frequency is f
SYS
divided by the value programmed into the
prescaler, the value of which is determined by bits PSC2~PSC0 or T0PSC2~T0PSC0 in the timer
control register. For TMR1 in theHT46R24/HT46C24, which has no prescaler, the input clock fre-
quency is f
SYS
/4. The timer-on bit, TON, T0ON or T1ON, depending upon which timer is used,
must be set high to enable the timer to run. Each time an internal clock high to low transition oc-
curs, the timer increments by one; when the timer is full and overflows, an interrupt signal is gener-
ated and the timer will preload the value already loaded into the preload register and continue
counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up
sources, however, the internal interrupts can be disabled by ensuring that the ETI or ET0I and
ET1I bits of the INTC register are reset to zero.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer pin, can
be recorded by the internal timer. For the timer to operate in the event counting mode, the bit pair,
TM1/TM0, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 0 and
1 respectively. The timer-on bit, TON, T0ON or T1ON, depending upon which timer is used, must
be set high to enable the timer to count. Depending upon which counter is used, if TE, T0E or T1E
is low, the counter will increment each time the external timer pin receives a low to high transition.
Chapter 1 Hardware Structure
39
I n c r e m e n t
T i m e r C o n t r o l l e r
T i m e r C l o c k o r
P r e s c a l e r O u t p u t
T i m e r + 1 T i m e r + 2 T i m e r + N T i m e r + N + 1
Timer Mode Timing Chart
T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r
T M R 1 C
N o t i m p l e m e n t e d , r e a d a s " 0 "
b 7
E v e n t C o u n t e r a c t i v e e d g e s e l e c t
1 : c o u n t o n f a l l i n g e d g e
0 : c o u n t o n r i s i n g e d g e
T 1 E T 1 O N T 1 M 0 T 1 M 1
b 0
T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e
1 : e n a b l e
0 : d i s a b l e
O p e r a t i n g m o d e s e l e c t
T 1 M 1
0
0
1
1
T 1 M 0
0
1
0
1
n o m o d e a v a i l a b l e
e v e n t c o u n t e r m o d e
t i m e r m o d e
p u l s e w i d t h m e a s u r e m e n t m o d e
P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t
1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e
0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e
N o t i m p l e m e n t e d , r e a d a s " 0 "