Holtek HT46R22, Руководство пользователя

Страница: 72 / 162

The various interrupt enable bits, together with their associated request flags, are shown in the fol-
lowing diagram with their order of priority.
Note In the figure, the T1F interrupt request flag and the ET1I interrupt enable bit refer to the HT46R24/
HT46C24 devices, which have two timers. For the HT46R47/HT46C47, HT46R22/HT46C22 and
HT46R23/HT46C23, which only have one timer, the Timer/Event Counter 0 represents the single
timer, known as TMR and has interrupt request flag known as TF and enable bit known as ETI.
External Interrupt
For an external interrupt to occur, the corresponding external interrupt enable bit must be first set.
This is bit 1 of the INTC or INTC0 register and shown as EEI. An external interrupt is triggered by a
high to low transition of the INT line, after which the related interrupt request flag (EIF; bit 4 of the
INTC or INTC0) will be set. When the interrupt is enabled, the stack is not full and the external inter-
rupt is active, a subroutine call to location 04H will occur. The interrupt request flag EIF will be re-
set and the EMI bit will be cleared to disable other interrupts.
Timer/Event Counter Interrupt
For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit
must be first set. In the case of devices with a single timer, this is bit 2 of the INTC or INTC0 register
and is known as ETI. For devices with two timers, the Timer 0 interrupt enable is bit 2 and known
as ET0I while the Timer 1 interrupt enable is bit 3 and known as ET1I. An actual Timer/Event Coun-
ter interrupt will be initialized when the Timer/Event Counter interrupt request flag is set, caused by
a timer overflow. In the case of devices with a single timer, this is bit 5 of the INTC or INTC0 regis-
ter and is known as TF. In the case of devices with two timers, the Timer 0 request flag is bit 5 and
known as T0F, while the Timer 1 request flag is bit 6 and known as T1F. When the master interrupt
global enable bit is set, the stack is not full and the corresponding internal interrupt enable bit is
set, an internal interrupt will be generated when the timer overflows. This will create a subroutine
call to location 08H for devices with a single timer. For devices with two timers, a subroutine call to
location 08H will occur for Timer 0 and a subroutine call to location 0CH for Timer 1. When an inter-
Chapter 1 Hardware Structure
63
A u t o m a t i c a l l y C l e a r e d b y I S R
M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e
E x t e r n a l I n t e r r u p t
R e q u e s t F l a g E I F
T i m e r / E v e n t C o u n t e r 0
I n t e r r u p t R e q u e s t F l a g T 0 F
T i m e r / E v e n t C o u n t e r 1
I n t e r r u p t R e q u e s t F l a g T 1 F
E E I
E T 0 I
E T 1 I
E M I
A u t o m a t i c a l l y D i s a b l e d b y I S R
C a n b e E n a b l e d M a n u a l l y
P r i o r i t y
H i g h
L o w
I n t e r r u p t
P o l l i n g
A / D C o n v e r t e r
I n t e r r u p t R e q u e s t F l a g A D F
I
2
C B u s
I n t e r r u p t R e q u e s t F l a g H I F
E A D I
E H I