Rev. 1.10
54
October 23, 2020
Rev. 1.10
55
October 23, 2020
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: 1. The EREN, ER, WREN, WR, RDEN and RD cannot be set high at the same time in one
instruction. The WR and RD cannot be set high at the same time.
2. Ensure that the f
SUB
clock is stable before executing the erase or write operation.
3. Ensure that the erase or write operation is totally complete before changing the contents of
the EEPROM related registers.
Read Operation from the EEPROM
Reading data from the EEPROM can be implemented by two modes for this device, byte read mode
or page read mode, which is controlled by the EEPROM operation mode selection bit, MODE, in
the EEC register.
Byte Read Mode
The EEPROM byte read operation can be executed when the mode selection bit, MODE, is cleared
to zero. For a byte read operation the desired EEPROM address should first be placed in the EEA
registers, as well as the read enable bit, RDEN, in the EEC register should be set high to enable the
read function. Then setting the RD bit high will initiate the EEPROM byte read operation. Note that
setting the RD bit high only will not initiate a read operation if the RDEN bit is not set high. When
the read cycle terminates, the EEPROM data can be read from the EED register and the RD bit will
automatically be cleared to zero. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Page Read Mode
The EEPROM page read operation can be executed when the mode selection bit, MODE, is set
high. The page size can be up to 16 bytes for the page read operation. For a page read operation
the start address of the desired EEPROM page must first be placed in the EEA register, as well as
the read enable bit, RDEN, in the EEC register should be set high to enable the read function. Then
setting the RD bit high will initiate the EEPROM page read operation. Note that setting the RD bit
high only will not initiate a read operation if the RDEN bit is not set high. When the current byte
read cycle terminates, the EEPROM data can be read from the EED register and then the current
address will be incremented by one by hardware. After this the RD bit will automatically be cleared
to zero. The data which is stored in the next EEPROM address can continuously be read from the
EED register when the RD bit is again set high without reconfiguring the EEPROM address and
RDEN control bit. The application program can poll the RD bit to determine when the data is valid
for reading.
The EEPROM address higher 3 bits are used to specify the desired page location while the lower
4 bits are used to point to the actual address. In the page operation mode the lower 4-bit address
value will automatically be incremented by one. However, the higher 3-bit address value will not
be incremented by hardware. When the EEPROM address lower 4-bit value which is internally
incremented by one in the page mode reaches the page boundary, known as 0FH, the EEPROM
address lower 4-bit value will stop at 0FH. The EEPROM address will not “roll over”.
Page Erase Operation to the EEPROM
The EEPROM page erase operation can be executed when the mode selection bit, MODE, is set
high. The EEPROM is capable of a 16-byte page erase. The internal page buffer will be cleared
by hardware after power on reset. When the EEPROM erase enable control bit, namely EREN, is
changed from “1” to “0”, the internal page buffer will also be cleared. Note that when the EREN bit
is changed from “0” to “1”, the internal page buffer will not be cleared. The EEPROM address lower
4 bits are internally incremented by one following the reception of each dummy data byte in the
