Hitachi DV-P345E, Руководство по обслуживанию

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SDATA[2] // I // SERVO channel sample data input for AFE by-pass //
PM[2] O Probe mux data output
149,147 GPCI/O[34-31] I/O General purpose input/output pins, monitored/controlled by the CPU or DSP
145,136 SW.
ICGPCI/O[5,4] I/O General purpose input/output pins monitored/controlled by the CPU or DSP
148,146 SW. When input, the pins can be used as general purpose external interrupts
to the CPU
IDGPCI/O[3] I/O General purpose input/output pins, monitored/controlled by the CPU or DSP
150 SW. When input, the pins can be used as general purpose external interrupts
to the DSP
PLL Signals (4 pins)
139 RESET# ID Reset input (active low)
142 GCLKP ID 27.000MHz clock or crystal input for main processing clock generation.
141 XO AO Output to a crystal that is connected to GCLK. If a crystal is not used at
GCLK, XO must be left not connected.
143 GCLKA ID 27.000MHz clock input for audio master clock generation. In normal operation
must be connected to GCLKP
Analog Video Port, (5 pins)
CVBS/G/Y AO When the I64 outputs composite video, this line is CVBS
158 (DAC A) When the I64 outputs RGB, this line is the Green output
When the I64 outputs YUV, this line is the Y output
Y/R/V/C AO When the I64 outputs the composite video, this line is Y
161 (DAC B) When the I64 outputs RGB, this line is the Red output
When the I64 outputs YUV, this line is the V output
When the I64 outputs SCART, this line is the C output
C/B/U AO When the I64 outputs the composite video, this line is C
162 (DAC C) When the I64 outputs RGB, this line is the Blue output
When the I64 outputs YUV, this line is the U output
159 CVBS/C/Y AO The output on this line can be either CVBS or C or Y
(DAC D) The selection is independent of the selection of the other three DACs.
163 RSET AI Resistive load for gain adjustment of the DACs
Digital Video Port, CPU, DSP and ADP de-bug (11 pins)
VID[7] // O // Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
ICETMS // I // ADP debug interface //
128 DJTMS // I // DSP debug interface //
GPCI/O[26] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
DACTEST[7] I DACs test input
VID[6] // O // Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
ICETDI // I // ADP debug interface //
129 DJTDI // I // DSP debug interface //
ICGPCI/O[2]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
to the CPU//
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