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No. 9403

MAIN BOARD SHEET 2

20

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Содержание DV-P345E

Страница 1: ...und Hinweise zurProduktsicherheit indiesemWartungshandbuchzulesen SERVICE MANUAL MANUEL D ENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alteration for improvement Les données fournies dans le présent manuel d entretien peuvent faire l objet de modifications en vue de perfectionner leproduit Die in diesem Wartungshandbuch enthaltenen Spezifikationen können sich ...

Страница 2: ... discs DVD ECC and EDC Track buffer and re try management Decoding Single chip solution for playback of DVD Video DVD Audio Video CD Super Video CD CD DA and MP3 from CD ROM CD R or CD R W Decoding and display of high resolution MPEG 1 and MPEG 2 still image sequences including ASVs from DVD Audio but without the transition effects Decoding of Dolby AC 3 DTS or MLP multi channel audio Decoding of ...

Страница 3: ...ront panel concentrator audio DACs and ADC etc e g using I2C SPI and other protocols 3 line serial general purpose slave interface SSC 2 UART interfaces for CPU SW debug JTAG interfaces for CPU ADP and DSP SW debug Physical Features Dual supply 1 8V for the core and PLL and 3 3V for the I O and DACs 208 pin PQFP package TTL I O levels 5V tolerance on many inputs Single 27MHz crystal clock input 5 ...

Страница 4: ...RT data input 152 GPCI O 35 I O General purpose input output pin monitored controlled by the CPU or DSP SW DUPTD1 O Second debug UART data output 156 GPCI O 38 I O General purpose input output pin monitored controlled by the CPU or DSP SW DUPRD1 I Second debug UART data input 155 GPCI O 37 I O General purpose input output pin monitored controlled by the CPU or DSP SW GPCI O 20 I O General purpose ...

Страница 5: ... composite video this line is Y 161 DAC B When the I64 outputs RGB this line is the Red output When the I64 outputs YUV this line is the V output When the I64 outputs SCART this line is the C output C B U AO When the I64 outputs the composite video this line is C 162 DAC C When the I64 outputs RGB this line is the Blue output When the I64 outputs YUV this line is the U output 159 CVBS C Y AO The o...

Страница 6: ...ltiplexed in time according to the CCIR656 standard for interlaced video or luma for progressive DJTDI I DSP debug interface 133 GPCI O 29 I O General purpose input output pin monitored controlled by the CPU or DSP SW DACTEST 2 I DACs test input SSEL 0 O SERVO channel select output for AFE by pass VID 1 O Digital video luma chroma output multiplexed in time according to the CCIR656 standard for in...

Страница 7: ...ed audio data 110 SDATA 3 I SERVO channel sample data input for AFE by pass PM 3 O Probe mux data output AOUT 2 1 O Serial outputs of digital stereo audio GPCI O 21 22 I O General purpose input output pin monitored controlled by the CPU or DSP 111 112 SW SDATA 4 5 I SERVO channel sample data inputs for AFE by pass PM 4 5 O Probe mux data outputs AOUT 0 O Serial output of digital stereo audio 113 S...

Страница 8: ... from RF amplifier 124 AFETESTN AI O AFE test differential signal input or output AFETESTN carries the negative Signal ADCIN 6 AI SERVO ADC input signal from RF amplifier 125 AFETESTP AI O AFE test differential signal input or output AFETESTP carries the positive Signal 178 183 ADCIN 5 0 AI SERVO ADC input signals from RF amplifier PWMCO 0 O PWM2 output signal GPCI O 41 I O General purpose input o...

Страница 9: ...al interrupt 201 to the CPU DVDVALID I AV data valid input for FE by pass Programmable polarity PM 16 O Probe mux data output SDRAM Interface 36 pins 103 100 98 94 90 88 85 8 2 84 86 89 92 96 99 102 104 RAMDAT 15 0 I O SDRAM bidirectional data bus 69 65 67 63 60 5 7 55 53 54 56 59 61 RAMADD 11 0 O SDRAM address bus output 74 RAMRAS O SDRAM row select active low output 75 RAMCAS O SDRAM column sele...

Страница 10: ...ress bus output 8 PLLCFGA I AFE test mode enable input Level sampled during RESET In normal operation the pin must be low during RESET MEMAD 11 O PNVM SRAM address bus output 10 PLLCFGP I Process PLL configuration input Level sampled during RESET In normal operation the pin must be low during RESET MEMAD 10 O PNVM SRAM address bus output 13 TESTMODE I Operational mode selection Level sampled durin...

Страница 11: ... 29 66 95 121 190 GNDC S Digital core ground of 1 8 V supply 5 pins 25 64 93 123 192 VDDC S 1 8 V Digital core power supply 5 pins 138 GNDA S Ground plane of internal PLL circuit 140 VDDA S 1 8 V Power supply for internal PLL circuit 160 VDDDAC S 3 3 V Analog power supply for the video DACs 164 GNDDACP S Grounds for the video DACs 3 3 V analog power supply 2 pins 157 GNDDACD 165 GNDDABS2 S Common ...

Страница 12: ...e The outputs of the DACs are differential not single ended so a buffering circuit is required The buffer circuit use a National LM833 op amp to perform the low pass filtering and the buffering 5 VPU VIDEO PROCESSING UNIT The VPU is responsible for all video output processing and timing It outputs 8 bit CCIR 656 type digital interlaced video and separate syncs It can also output interlaced composi...

Страница 13: ...e on chip 54 MHz DACs The fourth DAC has no output 6 FLASH MEMORY The decoder board supports 70ns Flash memories The CPU executes from a NOR type Flash memory with 16 bit data bus Alternately a compatible EPROM PROM OTPROM or masked ROM can be connected 7 SERIAL EEPROM MEMORY An I2C serial EEPROM is used to store user configuration i e language preferences speaker setup etc and software configurat...

Страница 14: ...nal clk54 the RF channel ADC sampling clock rf_clk and the servo ADC and DACs sampling clock adc_servo_clk The third unit is responsible to generate the internal reset signals to all I64 units after detecting a proper power up condition or a proper external reset input signal 10 FRONT PANEL 10 1 VFD CONTROLLER The VFD controller is a PTC PT6311 This controller is not a processor but does include a...

Страница 15: ... input with RGB inputs for example when inserting closed caption text It is called fast because this can be done at the same speeds as other video signals which is why it requires the same 75R impedances 0 to 0 4V TV is driven by the composite video input signal pin 19 Left unconnected it is pulled to 0V by its 75R termination 1V to 3V the TV is driven by the signals Red Green Blue and composite s...

Страница 16: ...voltage on the 5 volt winding constant 22 Volts is used to feed the VFD Vacuum Fluorescent Display driver IC on the front panel 12 2 FRONT PANEL All the functions on the front panel are controlled by IC1 ZR36768 on the mainboard IC1 sends the commands to IC2 PT6311 via socket PL1 pins 3 4 and 5 There are 16 keys scanning function 2 LED outputs 1 Stand by output and VFD drivers on IC2 Pin 52 is the...

Страница 17: ...evice is on Socket PL2 which is coming from the mainboard transmits RED GREEN BLUE and VIDEO signals to SCART over the buffer stage LUMA and CHROMA signals of S Video are transmitted to S Video socket via transistors Q25 Q29 Q26 Q30 respectively 13 SOFWARE UPDATE 13 1 Universal Service Password for Parental Level 1369 13 2 Version Page Hidden Menu To see Version Page Press DISPLAY button from remo...

Страница 18: ...uage Group 2 Note Update CD should have no volume ID 13 4 CD UPDATE PROCEDURE 1 Any Player can be updated automatically with Update CD which contains proper files see Service Cd Jpg 2 Burn up CD within proper files 2 There should be no Volume Name for CD 3 Open Tray and place update CD 4 You can see Upgrade File Detected Press Play to start OSD message 5 Press Play button to start upgrade 6 You ca...

Страница 19: ... selection can be seen under Preferences Setup Select Version or version Page 1st line contains release number like EFXX 5th line contains hardware options and build number Press DISPLAY button on remote control to exit hidden menu 13 5 Region Management At version Page by using arrow keys you can change region 14 CIRCUIT SCHEMATICS and PCBs Appendix A Downloaded Free from http www free service ma...

Страница 20: ...THE UPDATED PARTS LIST FOR THIS MODEL IS AVAILABLE ON ESTA Downloaded Free from http www free service manuals com ...

Страница 21: ...No 9403 MAIN BOARD SHEET 1 14 CIRCUIT SCHEMATICS 19 Downloaded Free from http www free service manuals com ...

Страница 22: ...No 9403 MAIN BOARD SHEET 2 20 Downloaded Free from http www free service manuals com ...

Страница 23: ...No 9403 MAIN BOARD SHEET 3 21 Downloaded Free from http www free service manuals com ...

Страница 24: ...No 9403 MAIN BOARD SHEET 4 22 Downloaded Free from http www free service manuals com ...

Страница 25: ...No 9403 MAIN BOARD SHEET 5 23 Downloaded Free from http www free service manuals com ...

Страница 26: ...No 9403 MAIN BOARD SHEET 6 24 Downloaded Free from http www free service manuals com ...

Страница 27: ...No 9403 MAIN BOARD SHEET 7 25 Downloaded Free from http www free service manuals com ...

Страница 28: ...No 9403 POWER SUPPLY BOARD 26 Downloaded Free from http www free service manuals com ...

Страница 29: ...No 9403 FP BOARD 27 Downloaded Free from http www free service manuals com ...

Страница 30: ...No 9403 MAIN BOARD COMPONENT TOP SIDE SOLDER BOTTOM SIDE 28 15 CIRCUIT BOARDS Downloaded Free from http www free service manuals com ...

Страница 31: ...WER FP SC BOARDS SOLDER BOTTOM SIDE COMPONENT TOP SIDE SCART BOARD COMPONENT TOP SIDE SOLDER BOTTOM SIDE FRONT PANEL BOARD POWER BOARD COMPONENT TOP SIDE 29 Downloaded Free from http www free service manuals com ...

Страница 32: ...39 02 487861 Tel 39 02 38073415 Servizio Clienti Fax 39 02 48786381 2 Email customerservice italy hitachi eu com HITACHI Europe AB Box 77 S 164 94 Kista SWEDEN Tel 46 0 8 562 711 00 Fax 46 0 8 562 711 13 Email csgswe hitachi eu com HITACHI EUROPE S A S Lyon Office B P 45 69671 BRON CEDEX FRANCE Tel 04 72 14 29 70 Fax 04 72 14 29 99 Email france consommateur hitachi eu com HITACHI EUROPE LTD Norway...

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