Hitachi DV-P345E, Руководство по обслуживанию

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The image post-processing unit can scale the stored image (horizontally and vertically with scale
ratios of 1/2 to 2) and shift it with 1/4 pixel resolution. Then, it can enhance the image and pad it
with background colour.
In addition, the VPU has a DVD sub-picture decoding unit. The sub-picture is blended with the
enhanced image. The resulting image is blended with an OSD image generated by a 2, 4 or 8 bits
per pixel OSD Decoder. Finally, closed captions is added to generate the final digital video.
The final interlaced digital video is processed by the video encoder to generate six 10 bit video
streams. One stream is composite video, the next two are the luma and composite chroma
components of the Svideo format. The three other streams are color components, either Y,U,V or
R,G,B. Four of the sixstreams are converted to analog by four on-chip 54 MHz DACs. For three of
the four DACs, the selected combination can be: (a) Interlaced composite and S-video; (b) Three
interlaced components (either Y,U,V or R,G,B); (c) Three progressive Y,U,V components. For
cases (a) and (b), the fourth DAC can output either the composite signal, the luma (Y) signal, or
the chroma (C) signal of the S-Video.
The final progressive digital video is processed by the video encoder to generate three 10 bit
video color components streams, either Y,U,V or R,G,B. The streams are converted to analog by
three on-chip 54 MHz DACs. The fourth DAC has no output.
6. FLASH M
EMORY
The decoder board supports 70ns Flash memories. The CPU executes from a NOR type Flash
memory with 16 bit data bus. Alternately, a compatible EPROM, PROM, OTPROM or masked
ROM can be connected.
7. S
ERIAL
EEPROM M
EMORY
An I2C serial EEPROM is used to store user configuration (i.e. language preferences,
speaker setup, etc.) and software configuration.. Industry standard EEPROM range in size from
1kbit to 256kbit and share the same IC footprint and pinout. The default device is 2kbit, 256kx 8,
SOIC8 CSI 24WC02 or equivalent.
8. ADP - A
UDIO
D
ATA
P
ROCESSOR
The ADP is the audio processing unit of the I64 . It is based on a 20 bits data and 32 bits
instruction ADP44 core. The ADP core has attached to it 24 KWords (32 bits) instruction and data
ROM, 5 Kwords (32 bits) instruction RAM, 8 KWords (20 bits) data RAM, 1 KWords (20 bits) data
DMA caches, and several peripheral units mentioned below.
The peripherals are DMA interface unit, audio code interface unit, CPU and DVP interface unit,
realtime clock unit, serial port unit, serial port PLL unit and interrupt handler.
All the ADP peripheral units are connected to the ADP core through the AP_Bus (audio
peripherals bus). The interrupt handler is also connected directly to the interrupt port of the ADP
core.
Several external pins (multiplexed with the digital video pins) can be used for debugging. This
interface is usually called "ICE" (which is of course a mis-nomer as ICE means "In-Circuit
Emulation") but they are similar to JTAG.
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