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12

Plasma TV Service Manual

11/01/2005

9.12. MSP34X1G

MSP3411G

Multistandard Sound Processor Family

9.12.1. Introduction

The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on
a single chip. Figure shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound
feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G
includes the Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby

1)

Laboratories for with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the
“PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo
Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard
automat-ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can
be evaluated internally with subsequent switching between mono/stereo/bilingual; no I

2

C interaction is

necessary (Automatic Sound Selection).

Source Select

I

2

S bus interface consists of five pins:

1. I

2

S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling

cycle (32 kHz) are transmitted.
2. I

2

S _DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.

3. I

2

S _CL: Gives the timing for the transmission of I

2

S serial data (1.024 MHz).

4. I

2

S _WS: The I

2

S _WS word strobe line defines the left and right sample.

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Содержание 42PMA225EZ

Страница 1: ...e Ingenieur die Sicherheitshinweise und Hinweise zur Produktsicherheit in diesem Wartungshandbuch zu lesen SERVICE MANUAL MANUEL D ENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alteration for improvement Les données fournies dans le présent manuel d entretien peuvent faire l objet de modifications en vue de perfectionner le produit Die in diesem Wartungshandbuc...

Страница 2: ...1 General Description 5 9 3 2 Features 5 9 4 ST24LC21 5 9 4 1 Description 5 9 4 2 Features 5 9 4 3 Pin connections 6 9 5 TLC7733 6 9 5 1 Description 6 9 6 74LVC257A 7 9 6 1 Features 7 9 6 2 Description 7 9 6 3 Pin Description 7 9 7 74LVC14A 7 9 7 1 Features 7 9 7 2 Applications 7 9 7 3 Description 7 9 7 4 Pin Description 8 9 8 TEA6420 8 9 8 1 Features 8 9 8 2 Description 8 9 9 LM1086 8 9 9 1 Descr...

Страница 3: ... PCF8591 26 9 19 1 General Description 26 9 19 2 Features 26 9 19 3 Pinning 27 9 20 PW1231 27 9 20 1 General Description 27 9 20 2 Features 27 9 20 3 Applications 28 9 21 PW181 28 9 21 1 General Description 28 9 21 2 Features 28 9 21 3 Applications 29 9 22 SIL151B 29 9 22 1 General Description 29 9 22 2 Features 29 9 23 SDRAM 4M x 16 MT48LC4M16A2TG 75 29 9 23 1 General Description 29 9 23 2 Featur...

Страница 4: ... video switch IC TEA6415 is used The main function of this device is to switch 8 video input sources on the 6 outputs Each output can be switched on only one of each input On each input an alignment of the lowest level of the signal is made bottom of sync top for CVBS or black level for RGB signals Each nominal gain between any input and output is 6 5dB For D2MAC or Chroma signal the alignment is ...

Страница 5: ...w external processor control of all internal functions 7 SERIAL ACCESS CMOS 4K x 8 32K bit EEPROM 24C32A The Microchip Technology Inc 24C32A is a 4K x 8 32K bit Serial Electrically Erasable PROM It has been developed for advanced low power applications such as personal communications or data acquisition The 24C32A also has a page write capability of up to 32 bytes of data The 24C32A is capable of ...

Страница 6: ...sary to determine one configuration 9 1 2 Features 20MHz Bandwidth Cascadable with another TEA6415C Internal address can be changed by pin 7 voltage 8 Inputs CVBS RGB MAC CHROMA 6 Outputs Possibility of MAC or chroma signal for each input by switching off the clamp with an external resistor bridge Bus controlled 6 5dB gain between any input and output 55dB crosstalk at 5 MHz Fully ESD protected 9 ...

Страница 7: ... Automotive E 40 C to 125 C 9 2 2 Description The Microchip Technology Inc 24C32A is a 4K x 8 32K bit Serial Electrically Erasable PROM It has been developed for advanced low power applications such as personal communications or data acquisition The 24C32A also has a page write capability of up to 32 bytes of data The 24C32A is capable of both random and sequential reads up to the 32K boundary Fun...

Страница 8: ...range 1 2 to 37V Output current In excess of 1 5A 0 1 Line and Load Regulation Floating Operation for High Voltages Complete Series of Protections Current Limiting Thermal Shutdown And Soa Control 9 4 ST24LC21 9 4 1 Description The ST24LC21 is a 1K bit electrically erasable programmable memory EEPROM organized by 8 bits This device can operate in two modes Transmit Only mode and I2 C bidirectional...

Страница 9: ...77xx has a fixed SENSE threshold voltage set by an internal voltage divider When SENSE voltage drops below the threshold voltage the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time td has expired In addition to the power on reset and under voltage supervisor function the TLC77xx adds power down control support for static RAM When ...

Страница 10: ...mentation of a 4 pole 2 position switch where the position of the switch is determined by the logic levels applied to S The outputs are forced to a high impedance OFF state when OE is HIGH 9 6 3 Pin Description PIN NUMBER SYMBOL DESCRIPTION 1 S Common data select input 2 5 11 14 1 0 to 4 0 Data inputs from source 0 3 6 10 13 1 1 to 4 1 Data outputs from source 1 4 7 9 12 1Y to 4Y 3 State multiplex...

Страница 11: ...6 9 9 1 Description The LM1086 is a series of low dropout positive voltage regulators with a maximum dropout of 1 5V at 1 5A of load current It has the same pin out as National Semiconductor s industry standard LM317 The LM1086 is available in an adjustable version which can set the output voltage with only two external resistors It is also available in five fixed voltages 2 5V 2 85V 3 3V 3 45V an...

Страница 12: ...nt limiting and thermal shutdown Its circuit includes a zener trimmed bandgap reference to as sure output voltage accuracy to within 1 The LM1117 series is available in SOT 223 TO 220 and TO 252 D PAK packages A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability 9 10 2 Features Available in 1 8V 2 5V 2 85V 3 3V 5V and Adjustable Versions Sp...

Страница 13: ...de high speed TTL interfaces 9 11 2 Features 20 to 85 MHz shift clock support Best in Class Set Hold Times on TxINPUTs Tx power consumption 130 mW typ 85MHz Grayscale Tx Power down mode 200µW max Supports VGA SVGA XGA and Dual Pixel SXGA Narrow bus reduces cable size and cost Up to 2 38 Gbps throughput Up to 297 5 Megabytes sec bandwidth 345 mV typ swing LVDS devices for low EMI PLL requires no ex...

Страница 14: ... R_FB I 1 Programmable strobe select HIGH rising edge LOW falling edge TxCLK OUT O 1 Positive LVDS differential clock output TxCLK OUT O 1 Negative LVDS differential clock output PWR DOWN I 1 TTL level input Assertion low input TRI STATES the outputs ensuring low current at power down Vcc I 3 Power supply pins for TTL inputs GND I 5 Ground pins for TTL inputs PLL Vcc I 1 Power supply pin for PLL P...

Страница 15: ... standard recommended by the Broadcast Television Systems Committee BTSC The DBX noise reduction or alternatively Micronas Noise Reduction MNR is performed alignment free Other processed standards are the Japanese FM FM multiplex standard EIA J and the FM Stereo Radio standard Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA J The MSP 34...

Страница 16: ... if not used leave vacant OBL obligatory connect as described in circuit diagram DVSS if not used connect to DVSS AHVSS connect to AHVSS Pin No Pin Name Type Connection if not used Short Description PLCC 68 pin PSDIP 64 pin PSDIP 52 pin PQFP 80 pin PLQFP 64 pin 1 16 14 9 8 ADR_WS OUT LV ADR word strobe 2 NC LV Not connected 3 15 13 8 7 ADR_DA OUT LV ADR Data Output 4 14 12 7 6 I2S_DA_IN1 IN LV I2 ...

Страница 17: ...nnected 44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN 45 39 33 39 31 AHVSUP OBL Analog power supply 8V 46 38 32 38 30 CAPL_A OBL Volume capacitor AUX 47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1 left 48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1 right 49 35 29 35 27 VREF1 OBL Reference ground 1 50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2 left 51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2 ...

Страница 18: ...ped for portable digital audio applications It gets its input from two analog audio outputs DACA_L and DACA_R of MSP 34x0G The gain of the output is adjustable by the feedback resistor between the inputs and outputs 9 13 2 Features Wide temperature range No switch ON OFF clicks Excellent power supply ripple rejection Low power consumption Short circuit resistant High performance high signal to noi...

Страница 19: ...ly analog input and Hsync and COAST signals Three state CMOS outputs may be powered from 2 5 V to 3 3 V The AD9883A s on chip PLL generates a pixel clock from the Hsync input Pixel clock output frequencies range from 12 MHz to140 MHz PLL clock jitter is 500 ps p p typical at 140 MSPS When the COAST signal is presented the PLL maintains its output frequency in the absence of Hsync A sampling phase ...

Страница 20: ...3 Power Supply VD VDD PVD GND Analog Power Supply Output Power Supply PLL Power Supply Ground 3 3 V 3 3 V 3 3 V 0 V 39 42 45 46 51 52 59 62 11 22 23 69 78 79 26 27 34 35 1 10 20 21 24 25 28 32 36 40 41 44 47 50 53 60 61 63 68 80 Control SDA SCL A0 Serial Port Data I O Serial Port Data Clock 100 kHz Maximum Serial Port Address Input 1 3 3 V CMOS 3 3 V CMOS 3 3 V CMOS 57 56 55 Pin Function Descripti...

Страница 21: ... Horizontal Sync Input This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation The logic sense of this pin is controlled by serial register 0EH Bit 6 Hsync Polarity Only the leading edge of Hsync is active the trailing edge is ignored When Hsync Polarity 0 the falling edge of Hsync is used When Hsync Polari...

Страница 22: ...e minimize noise and parasitics on this node POWER SUPPLY VD VDD PVD GND Main Power Supply These pins supply power to the main elements of the circuit They should be filtered and as quiet as possible Digital Output Power Supply A large number of output pins up to 25 switching at high speed up to 110 MHz generates a lot of power supply transients noise These supply pins are identified separately fr...

Страница 23: ...ontrol AGC matching to the particular signal properties On chip line locked clock generation in accordance with ITU 601 Requires only one crystal 32 11 or 24 576 MHz for all standards Horizontal and vertical sync detection Video decoder Digital PLL for synchronization and clock generation from all standards and non standard video sources e g consumer grade VTR Automatic detection of any supported ...

Страница 24: ...e FIFO register for video output data 28 word 4 byte FIFO register for decoded VBI data output Scaled 4 2 2 4 1 1 4 2 0 4 1 0 Y CB CR output Scaled 8 bit luminance only and raw CVBS data output Sliced decoded VBI data output Miscellaneous Power on control 5 V tolerant digital inputs and I O ports Software controlled power saving standby modes supported Programming via serial I 2 C bus full read ba...

Страница 25: ...r testing TEST11 C14 I pu do not connect reserved for future extensions and for testing scan input AI43 D1 I analog input 43 AI42 D2 I analog input 42 AI4D D3 I differential input for ADC channel 4 pins AI41 to AI44 VDDA4 D4 P analog supply voltage for analog inputs AI4x 3 3 V VSSD1 D5 P Digital ground 1 peripheral cells TMS D6 I pu test mode select input for boundary scan test or scan test note 2...

Страница 26: ...IPD5 J14 O MSB 2 of image port data output AI12 K1 I analog input 12 AI13 K2 I analog input 13 AI1D K3 I differential input for ADC channel 1 pins AI14 to AI11 VDDA1 K4 P analog supply voltage for analog inputs AI1x 3 3 V IPD7 K11 O MSB of image port data output IGPH K12 O multi purpose horizontal reference output signal image port controlled by subaddresses 84H and 85H IGP1 K13 O general purpose ...

Страница 27: ... for analog to digital conversion of VSB signals 36 MHz ADP5 N7 O MSB 3 of direct analog to digital converted output data VSB ADP0 N8 O LSB of direct analog to digital converted output data VSB SCL N9 I serial clock input I 2 C bus RTS1 N10 O real time status or sync information controlled by subaddresses 11H and 12H ASCLK N11 O audio serial clock output ITRDY N12 I target ready input for image po...

Страница 28: ...regulators capable of providing the same output current this family of regulators can provide a stand alone power supply solution or a post regulator for a switch mode power supply These regulators are ideal for higher current applications The family operates over a wide range of input voltages 1 8 V to 6 V and has very low dropout 170 mV at 1 A Ground current is typically 210 µA at full load and ...

Страница 29: ...ield disturbance Suitable burst length 6 cycles burst Special Features Small size package Enhanced immunity against all kinds of disturbance light No occurrence of disturbance pulses at the output Short settling time after power on 200_s 9 19 PCF8591 9 19 1 General Description The PCF8591 is a single chip single supply low power 8 bit CMOS data acquisition device with four analog inputs one analog...

Страница 30: ... analog output D A converter VDD 16 positive supply voltage 9 20 PW1231 9 20 1 General Description The PW1231 is a high quality digital video signal processor that incorporates Pixelworks patented deinterlacing scaling and video enhancement algorithms The PW1231 accepts industry standard video formats and resolutions and converts the input into any desired output format The video algorithms are hi...

Страница 31: ...dded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on chip A separate memory is dedicated to storage of on screen display images and CPU general purpose use Advanced video processing techniques are supported using the internal frame buffer including motion adaptive temporal deinterlacing with film mode detection When used in combi...

Страница 32: ...containing 67 108 864 bits It is internally configured as a quad bank DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal CLK Each of the x4 s 16 777 216 bit banks is organized as 4 096 rows by 1 024 columns by 4 bits Each of the x8 s 16 777 216 bit banks is organized as 4 096 rows by 512 columns by 8 bits Each of the x16 s 16 777 216 bit banks is ...

Страница 33: ...4 8 or full page Auto Precharge includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes Self Refresh Modes standard and low power 64ms 4 096 cycle refresh LVTTL compatible inputs and outputs Single 3 3V 0 3V power supply 9 23 3 Pin Descriptions PIN NUMBERS SYMBOL TYPE DESCRIPTION 38 CLK Input Clock CLK is driven by the system clock All SDRAM input signals are sampled on the positive edge of CLK ...

Страница 34: ...nk Address Inputs BA0 and BA1 define to which bank the ACTIVE READ WRITE or PRECHARGE command is being applied 23 26 29 34 22 35 A0 A11 Input Address Inputs A0 A11 are sampled during the ACTIVE command row address A0 A11 and READ WRITE command column address A0 A9 x4 A0 A8 x8 A0 A7 x16 with A10 defining auto precharge to select one location out of the memory array in the respective bank A10 is sam...

Страница 35: ...nature or Block Protection status Programming Block and Chip Erase Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings 9 24 2 Features 2 7V to 3 6V Supply Voltage for Program Erase and Read Operations Access Time 80ns Programming Time 10µs typical Program Erase Controller P E C Program Byte by Byte or Word by W...

Страница 36: ...vice menu press M button Entire service menu parameters of Plasma TV are listed below 10 1 display menu By pressing buttons select the first icon display menu appears on the screen blank colour By pressing button select blank colour Press button to set the blank colour The options are black red green and blue panel Displays panel resolution power on time Displays total working time of the set back...

Страница 37: ...ssing button select subwoofer corner Press button to set the subwoofer corner Subwoofer corner can be adjusted between 0 and 7 subwoofer level By pressing button select subwoofer level Press button to set the subwoofer level Subwoofer level can be adjusted between 0 and 32 agc adjustment Adjustment for automatic gain control of tuner By pressing button select agc adjustment Press button to set the...

Страница 38: ...ed Green or Blue Press button to increase the colour temperature Press button to decrease the colour temperature Colour temperature can be adjusted between values 0 and 63 video format By pressing button select video format Press button to set the video format The options are auto ntsc pal secam and ntsc japan colour space Displays the current colour space used RGB YPbPr SMPTE240 YPbPr REC709 and ...

Страница 39: ...buttons select the third icon deinterlacer menu appears on the screen blank expansion By pressing button select blank expansion blank expansion can be set to on or off by pressing button dcti Digital colour transition improvement By pressing button select dcti DCTI can be adjusted between 0 and 255 by pressing button dlti Digitial luma transition improvement By pressing button select dlti DLTI can...

Страница 40: ... set to low or high by pressing button noise reduction By pressing button select noise reduction Noise reduction can be adjusted between 0 and 255 by pressing button lai level By pressing button select lai level Lai level can be set to 0 1 or 2 by pressing button sharpness By pressing button select sharpness Sharpness can be adjusted between 0 and 255 by pressing button sparkle By pressing button ...

Страница 41: ...OLOUR TEMPERATURE 6500 COLOUR TEMPERATURE USER 6500 VIDEO FORMAT AUTO COLOUR SPACE autodetected TEST PATTERN none COLOUR COMPONENTS all SOLID FIELD LEVEL 33 CALIBRATION INITIAL APS on BLACK EXPANSION DCTI DLTI LUMINANCE PEAKING FILM MODE FILM MODE SPEED VOF BAD CUT NR THRESHOLD NOISE REDUCTION LAI LEVEL SHARPNESS DEINTERLACER SPARKLE These values are not recorded for this reason they are adjusted ...

Страница 42: ...ESSOR MAIN PICTURE PHILIPS SAA7118E VIDEO PROCESSOR PIP PICTURE PHILIPS PW181 AUDIO VIDEO GRAPHICS IN OUT AUDIO AMPL BOARD 2 LAYER MAIN BOARD 6 LAYER DS090C385 LVDS Tx NATIONAL 24 bit RGB I2C HS VS DE CLK AD9883 ANALOG DEVICE ADC SIL151 SILICON DVI Rx YUV 16 bit YUV 16 bit 24 bit RGB 48 bit dual RGB PW1231 RG B 24 bit GENERAL BLOCK DIAGRAM IMAGE ...

Страница 43: ...IPS IF IC 1 TDA9886 I2C I2C IF 1 TUN1_CVBS TUN1_QSS1 SC1_V_OUT PHILIPS IF IC 2 TDA9886 IF 2 TUN2_CVBS TO TEA6415 VIDEO SWITCH TO MSP3411G AUDIO PROCESSOR FOR MAIN SOUND TO TEA6415 PIP VIDEO SWITCH A V BOARD 6 layer SC3_V_OUT TUN2_QSS2 TO MSP3411G AUDIO PROCESSOR FOR PIP SOUND TUNER IF BLOCK ...

Страница 44: ...41 Plasma TV Service Manual 11 01 2005 VIDEO MATRIXING ...

Страница 45: ...42 Plasma TV Service Manual 11 01 2005 AUDIO MATRIXING ...

Страница 46: ......

Страница 47: ...W1231 DE INTERLACER 24 bit RGB SVIDEO1_C SVIDEO1_Y SVIDEO1_C SVIDEO1_Y TXT CC_FB TXT CC_R TXT CC_G TXT CC_B TXT CC_FB TXT CC_R TXT CC_G TXT CC_B TXT CC_R TXT CC_G TXT CC_B 16 bit YUV Progressive or Interlaced 24 bit dual RGB HS VS DE PCLK Parity PC_R_IN PC_G_IN PC_B_IN PC_HS PC_VS SC_B SC_G SC_R SC_FB PI5 V330 SCART1 RGB FB SCART2 RGB FB SC_B SC_G SC_R SC_FB PI5 V330 SCART1 RGB FB SCART2 RGB FB VI...

Страница 48: ...4 PHILIPS CVBS_ for TELETEXT TXT CC_R TXT CC_FB TXT CC_G TXT CC_B FROM VIDEO SWITCH INTO SAA7118 RGB FB PORTS PIN 8 SWITCHING PCF8591 SC2 PIN8 SC2 PIN8 SC3 PIN8 SC3 PIN8 SC1 PIN8 SC1 PIN8 SC4 PIN8 SC4 PIN8 I2C COMMUNICATION TELETEXT DECODING PIN8 SWITCHING ...

Страница 49: ...ART 1 CVBS INPUT 2 SCART 2 CVBS INPUT 3 SCART 1 RGB FB INPUT 4 SCART 2 RGB FB INPUT 5 FAV IN 6 FRONT SVHS IN 7 VGA INPUT 8 DVI INPUT 9 PC AUDIO INPUT 10 MAIN TUNER 11 PIP TUNER 1 SCART 1 CVBS OUT 2 SCART 2 CVBS OUT 3 AUDIO LINE OUT INPUT OUTPUTS ...

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Страница 60: ...47 Milano Italia ITALY Tel 39 02 487861 Tel 39 02 38073415 Servizio Clienti Fax 39 02 48786381 2 Email customerservice italy hitachi eu com HITACHI Europe AB Box 77 S 164 94 Kista SWEDEN Tel 46 0 8 562 711 00 Fax 46 0 8 562 711 13 Email csgswe hitachi eu com HITACHI EUROPE S A S Lyon Office B P 45 69671 BRON CEDEX FRANCE Tel 33 04 72 14 29 70 Fax 33 04 72 14 29 99 Email france consommateur hitachi...

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