Hitachi 42PMA225EZ, Руководство по обслуживанию

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Plasma TV Service Manual 11/01/2005
9.11. DS90C385
9.11.1. General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signalling) data streams. A phase-locked transmit clock is transmitted in parallel with the
data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock
frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz
clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of
LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signalling) data streams. Both
transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver
(DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which
provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal
means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
9.11.2. Features
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost
• Up to 2.38 Gbps throughput
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
9.11.3. Pin Description
DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter
Pin Name
I/O No. Description
TxIN I 28
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O 4 Positive LVDS differentiaI data output.
TxOUT-
O 4
Negative LVDS differential data output.
TxCLKIN
I 1 TTL Ievel clock input. Pin name TxCLK IN.
R_FB
I 1
Programmable strobe select
TxCLK OUT+ O 1
Positive LVDS differential clock output.
TxCLK OUT- O 1 Negative LVDS differential clock output.
PWR DOWN
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
Vcc
I 3 Power supply pins for TTL inputs.
GND
I 4
Ground pins for TTL inputs.
PLL Vcc I 1 Power supply pin for PLL.
PLL GND I 2
Ground pins for PLL.
LVDS Vcc
I 1 Power supply pin for LVDS outputs.
LVDS GND
I 3
Ground pins for LVDS outputs.