
103
&
&
&
7.15 Standard
Event
Status
Register
After mask processing by the Standard Event Status Enable register, messages are
concentrated in the ESB bits of the Status Byte register.
The following is messaged related to the Standard Event Status register.
*CLS
Clears the following registers:
· Status byte register
· Standard Event Status register
· Device Event Status Register
· Error register
*ESE
Sets the Standard Event Status Enable register
*ESE?
Queries the Standard Event Status Enable register
*ESR?
Queries and clears the Standard Event Status register
Standard Event
Standard Register
Standard Event
Standard Enable Register
ESBs of Status Byte Register
PON
:
Power On
URQ
:
User Request
CME
:
Command Error
EXE
:
Execution Error
DDE
:
Device Dependent Error
QYE
:
Query Error
RQC
:
Request Control
OPC
:
Operation Complete
Fig. 7.6 Configuration of Standard Event Status Register
PON
7
URQ
6
CME
5
EXE
4
DDE
3
QYE
2
RQC
1
OPC
0
Logical
OR
PON
7
URQ
6
CME
5
EXE
4
DDE
3
QYE
2
RQC
1
OPC
0
&
&
&
&
&
Содержание DSM-8542
Страница 1: ...DIGITAL SUPER Instruction Manual DSM 8542 July 2013 Revised edition 1 DS8542A981 01 13 07H MEGOHMMETER...
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Страница 21: ...11 3 2 Block Diagram of DSM 8542...
Страница 89: ...79 Syntax Chart Fig 7 1 Message Syntax Chart...
Страница 90: ...80 Command program header Fig 7 2 Program Header Syntax Chart...
Страница 91: ...81 Fig 7 3 Syntax Chart of Data Part...
Страница 138: ...128 11 Product Full View...
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