Hioki 9518-02, Инструкция по эксплуатации

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4.13 Event Registers
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＆ ＆ ＆ ＆ ＆ ＆ ＆
UnusedUnused
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EOM LFAIL UFAIL PASS UnusedUnused
UnusedUnused
bit 7
bit 6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
EOM LFAIL UFAIL PASS UnusedUnused
bit 0
ESB0
Event status register 0 (ESR0)
Event status enable register 0 (ESER0)
Logical sum
Status byte register (STB)
Event status register 0 (ESR0) bit assignments
Bit 7 Unused
Bit 6 Unused
Bit 5 Unused
Bit 4 Unused
Bit 3
EOM
Test completed
Bit 2
LFAIL
Below lower limit of comparator
Bit 1
UFAIL
Above upper limit of comparator
Bit 0
PASS
Within limits of comparator
(3) Event status register specific to the 3157 (ESR0)
An 8-bit event status register is provided for managing events on the 3157. If
any bit in this event status register is set to 1 (after masking by the
corresponding event status enable register), the following happens:
・ For event status register 0, bit 0 of the status byte register (ESB0) is set to 1.
Event status register 0 is cleared in the following three situations:
When a "*CLS" command is received.
When an ":ESR0?" query is received.
When the unit is powered on.
(4) Event status enable register specific to the 3157 (ESER0)
This event status enable register masks the corresponding event status
register.