Highland T560, Техническое руководство, Страница: 12 / 49

12 T560MANK5.DOCX
3.4. Trigger Inputs
Figure 3.2 is a simplified diagram of the T560 trigger and sequence logic. Any one of five
available trigger sources may be selected to fire the system: E, External-, an
internal 80-MHz clock, the internal 0-16 MHz DDS synthesizer, and the user software
trigger. The selected trigger is divided by a programmable factor K from 1 to 2^32-1 and
supplied to the cycle-start HIT flipflop. The hit flopflop is enabled by the gating/burst logic.
Once the flipflop is fired, eight identical timing blocks generate delays A1 through D2, each
programmable from 0 to 20 seconds in 10-ps steps. Pairs of delays are combined to result
in four outputs, each a pulse whose delay and width are programmable with respect to the
common trigger. When all delay blocks have timed out, the EOD (end-of-delay) logic resets
the hit flipflop for about 50 ns, after which the system is enabled to accept another trigger.
The standard external trigger is a positive level, with trigger threshold programmable from
+0.25 to +3.3 volts and selectable rising/falling edge. The trigger input may be programmed
to be high impedance or a 50-ohm termination to ground. Maximum safe input levels are -
0.3 to +5.0 volts.
The maximum allowed trigger rate is
R = 1 / (D + W + 60 ns)
where D + W is the greatest channel sum of programmed delay plus width, and R is limited
to 16 MHz max. If a channel is programmed OFF, its time settings are not relevant. If the
T560 receives an internal or external trigger while a timing cycle is still busy, that trigger will
be ignored.
An internal 80 MHz clock (exactly 8x the main 10 MHz clock) may also be selected as the
trigger source. When it is used, a trigger divisor K must be programmed to keep the trigger
rate at or below 16 MHz.
The internal DDS synthesizer allows internal triggering at rates from 0 to 16 MHz with 0.02-
Hz resolution. The DDS synthesizer has a period jitter of about 1 part in 20,000, which can
be substantial in absolute terms at lower requested frequencies. Both period jitter and
resolution can be improved by keeping the DDS frequency in the 2-10 MHz range and
using the internal trigger divisor facility to get lower trigger rates.
External triggers up to 125 MHz can be accepted, given that a programmed divisor or the
inherent busy-cycle limitation will restrict the actual trigger rate to some countdown fraction
of the input frequency below 16 MHz.