31
6.1
Typical Jitter Performance
1.0E-12
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
DELAY (s)
R
M
S
J
IT
T
E
R
(
s
)
Figure 15. Typical RMS Jitter
Figure 15 is a graph of typical RMS jitter as a function of programmed delay. The
measurement was made using a 2-volt asynchronous external trigger from a
Tektronix PG-502 pulse generator, with delay measured on a type 11801 sampling
oscilloscope. At longer delays, the oscilloscope jitter increases to unusable levels, so
longer delays were measured by using the scope to characterize the jitter between
two independent P400s programmed to generate slightly different delays. The delay
increase beginning around 10 milliseconds is a result of the phase noise of the TCXO
timebase internal to the P400. The OCXO timebase option moves this corner out by
at least 10:1.
Note that jitter increases for delays from 0 to about 3
µ
s, at which time the DSP
phase lock system begins to discipline the 50 MHz gated oscillator.