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3
Theory of Operation
3.1
Basic Timing
Figure 1 depicts the basic P400 timing cycle.
Figure 1. Example Timing Diagram
A timing cycle begins 25 ns after a trigger pulse is received. T0 is asserted,
transitioning from VL (programmed low level) to VH (programmed high level),
indicating the start of the timing cycle. After the initial delay, each channel’s output is
asserted, transitioning from VL to VH or VH to VL, depending on the output polarity.
Channel timing is relative to the leading edge of T0, not to the trigger pulse.
When the last channel is deasserted, the T0 output falls, transitioning from VH to VL.
At this point, end-of-delay (EOD) is declared and the internal EOD signal is asserted
for approximately 50 ns. During this time, all outputs are reset to their default state,
the 50 MHz oscillator is disabled, the HIT flip-flop is held in reset and the T0 output is
