Hand Held Products IMAGETEAM IT4000HD, Руководство по интеграции

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IMAGETEAM™ 4X00 Series Integration Manual B - 1
B
FIFO Depth Based on System Assessment
The depth of the FIFO for the image capture system with DMA to main system memory is dependent on many factors that govern
the system performance, and may be different for every design. FIFO depth must equal the number of memory bytes needed
to store all image data acquired during the longest system delay (latency) that restricts DMA access to the bus, based on an
image acquisition rate of 13.5MB/s.
FIFO_Depth(bytes) = T
sys
/ T
pix
The latencies for systems vary for many reasons. You need to understand the system operation and delays before setting the
optimum depth, or be able to reconfigure the depth as the latencies are identified. The following is a list of system criteria
(reasons) that directly affect the FIFO depth decision. The longest possible system latency may be the total of any or all of these
delay sources.
Operating System The overhead of the OS plays a major role in determining bus and DMA availability to move data
from the FIFO to main memory.
Interrupt Service
Routine Latency Typically an ISR does not allow other activities, like DMA, to occur while the interrupt is being
handled. This happens in a system running high priority real time interfaces with IRQs.
Bus Turnaround This is the time it takes the processor to release the bus from a bus request, or to service a DMA
request. This includes the time to complete the current instruction or task, and all memory timing
(RAM or ROM) associated with fetching code and reading or writing data.
DMA Startup The time it takes the DMA to initialize and begin moving the image data.
Other DMA Transfers The time to complete other DMA transfers that may have a higher priority than the image transfer
DMA. For example, a DMA transfer to avoid a serial buffer overflow.
Memory Startup
Timing The access time (startup time for DRAM) to the first transfer of image data.
T
IRQ/ISR
+ T
OS
+ T
DMA_Seriall
+ T
BTA
+ T
DMASu
+ T
MSuT
= (T
pix
x FIFO_Depth)
The delay sources listed above are just a few of the basic latency sources of any given system. Each system has its own set of
characteristics, design criteria and design choices that affect the total system latency. You have to identify the behavior of the
design at hand and size the FIFO accordingly.