Hand Held Products IMAGETEAM IT4000HD, Руководство по интеграции

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2 - 2 IMAGETEAM™ 4X00 Series Integration Manual
I
2
C Style Interface Basic Waveforms
The following information is provided for reference. The I
2
C-Bus Specification should be consulted for a complete understanding
of the this interface.
Timing Chain
Control Register Table
*Value is 20 pixels > 640 active plus 10 light shielded pixels to ensure a good dark region for CDS subtractive pulse sample.
**5 lines > active plus 10 light shielded lines.
Vertical Considerations
When you change the value of the row start register you do not delay the data output. The value of this register sets a row pointer
that is allowed to roll over. The result is the output of all data from frame 10 during the frame 10 scan out period.
Example: If the row start value is set to 520 in a 525 row frame, then the active row number 4 of frame 10 is actually seen at
the beginning of frame 10 (not 11), and the first 5 lines of frame 10 occur at the end of 10. This means that a
movement of the active row start appears as a delay in time until the value set in registers 0x15, 0x14 reaches a
number that, when added to the active row count of 490, is greater than the frame height. Therefore, a start row of
50 causes the last 15 active rows to be output first, followed by 35 inactive rows, then the first 475.
525 - (490+50) = -15
Control Register
Address
Description Min/Max (Dec)
0x0D,0x0C Frame Width (columns/pixel clocks) 670* / 1023
0x0E, 0x0f Frame Height (rows/lines) 495** / 1023
0x11, 0x11 Column to start output of active pixels 0 / 1023
0x15, 0x14 Row to start output of active pixels 0 / 1023
0x19, 0x18 Hsync end column (width) 1 / FW-1
0x1A,0x1B Vsync end row (width) 1 / FH-1
0x9C, 0x9B CDS Subtractive Pulse Column position 1 / FW-1
Stop
SCL
SDA
Start
Sp 8 9
ACK
St
2 2 1
ACK
SCL
8
SDA
1 9
Start and Stop condition waveforms:
Data Transfer waveforms: