Users Manual
Model 3600
www.globalspecialties.com
Page 18
user takes samples using the inner clock to inner code generator, this
also belongs to “synchronous sampling.”
If state sampling is used as the sampling clock signal in a measured
system, it is required to connect to special input channel clk1 or clk2.
Otherwise the sampling will not start. If the noise in the external
clock signal is too large, adjust the threshold voltage settings of the
external clock to obtain a pure clock signal. If the sampling clock
signal is poor, the sampled data cannot be used and the external clock
signals will not be stored to allow access to the displayed waveforms.
It will then be impossible to know the quality of the clock signals after
passing through threshold voltage comparator. A substitute method:
press
【
source
】
to select the aim source and use the inner clock as
the timing sampling. Then connect external clock signal to the special
clock channels clk1 and clk2. Now the external clock can take samples
to external clock signals. Clk1 and clk2’s timing waveforms display in
30~31 channels after sampling. When adjusting the threshold voltage
settings of the external clock, one can use the two channels to monitor
the adjustment effect.
Sampling mode can be set with the
【
Time/State
】
key, inner clock for
timing sampling and the external clock for state sampling. The external
clock contains external clk1 and external clk2. The default setting is the
timing sample using the internal clock.
Clock Limitations
To view variations of tested signal, a higher sampling velocity should be
used, however this may greatly increase the amount of data stored in
memory. Also the tested signal may be single/occasional and included
in a long data stream. To effectively capture these signals, it is necessary
to lengthen the time of the sampling. Again, this causes a greater
amount of data to be stored in memory. Considering memory space has
its limitations, there is a solution. Model 3600 sets two external clocks
into a logic “and” and logic “or” mode. This limits an external clock by
using another external clock. For example, select the logic “and” of two
external clocks as the sampling clock. Use the high level of the external
clk1 as the limit condition. Only when external clk1 is at a high level can
the sampling clk2 be opened. Then the sampling of data will run. All
other times the clk2 is shut down and no sampling will occur. If the set
limit conditions are suitable, it ensures that the unit only captures the
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