Users Manual
Model 3600
www.globalspecialties.com
Page 17
value difference between the two points. After finishing this type of
measurement , press
【
cursor 2
】
key to recall it into display window and
begin the next measurement.
Data Listing Cursor
In the Data Listing interface, cursor1, cursor2 and cursor measurement
are the same as the cursors in the Timing Waveform interface. The
difference is that the cursors in the timing waveform display are vertical
cursor lines, but in the data listing display interface, the cursors are
horizontal white rows in the display. There is only an address display of
two cursor rows regarding the parameter display under the data listing
(data values are contained the listing).
Sampling Setting
Model 3600 uses the sampling mode for obtaining data. This procedure
involves sampling to a digital input, not collecting a sample to the
input signal directly. Instead it digitally generates data points through
comparison and distinguishes between input signals and thresholds. It
then stores sampled data in memory which requires properly setting
the sampling parameters.
Sampling Mode
There are two sampling modes for this logic analyzer. One is timing
sample which collects samples of the external signals using the internal
equal time interval clock. The sampled data is equal time interval data,
in other words it takes “time” as the independent variable. The timing
waveforms after sampling will basically reflect the changes of the
tested signal as time. This approach is known as the timing analysis,
but the sampling clock and the tested system are independent of each
other and not synchronous and called “asynchronous sampling.”
The other sampling mode is the state sample which collects samples
using the clock of the system under test. The clock utilizes equal or
random time intervals. The sampling clock pulse can be seen as a
discrete event. Take the “event” sequences as independent variables.
The data listing after sampling reflects the logic state relation between
the system clock and the other signals in the system. This mode is
known as state analysis. Here, the sampling clock is synchronous with
the system under test and is also called “synchronous sampling.” If the
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