C2K User’s Guide
4-1
Chapter 4: Functional Blocks
4.1 Processor
The C2K is driven by the MPC7447A /MPC7448 PowerPC G4 processor, a high-performance,
superscaler, low-power, 32-bit processor based on PowerPC RISC architecture. The processor
core can run at speeds from 500MHz to 1.4GHz, and includes separate 32kB L1 instruction and
data caches. It also includes an on-chip 512kB/1MB L2 cache.
The MPC7448 processor is connected to the MV64460 PowerPC System Controller through a
64-bit 167MHz system bus operating in MPX mode. The system bus provides address decoding,
data transfer operations, and interrupt signaling.
4.2 DDR SDRAM
The C2K provides system memory in configurations of 512MB on the standard build, or 256MB,
or 1GB densities available as build options. The DDR SDRAM is organized in a memory array of
one bank (256MB/512MB) or two banks (1GB) of devices. System memory is controlled by the
MV64460’s DDR SDRAM Memory Controller through a 64-bit 167MHz Memory Bus. System
memory includes full Error Checking and Correction (ECC) protection with one bit error detect
and correct; multiple bit error detect and report functions.
4.3 Flash Memory
The C2K includes 64–512MB of flash memory configured in one 32-bit bank of 8-bit Spansion
MirrorBit™ flash ROM devices. The flash devices are located on the 32-bit asynchronous parallel
Device Bus, mastered by the MV64460 System Controller. The processor can read, erase, and
program the contents of flash memory.
4.3.1 Flash Write Protection
Operating firmware can write and erase data from the flash devices. Each flash device provides
‘chip erase’ functionality as well as separate erase and write protection of sectors. The C2K
provides several write-protect mechanisms to prevent boot code data loss during power cycling
and system initialization. Flash write-protection functions are OR’ed together so that any
write-protection function can override other write-protection functions for that area of flash.
The C2K provides the following write-protection options:
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