C2K User’s Guide
5-42
Resources
Counter Interrupt Status Register
The Counter Interrupt Status Register provides interrupt status information for each counter.
7
CNTR7_INT_MSK
1
Counter 7 Interrupt Mask—blocks (masks) the interrupt for
counter 7.
0 = enable interrupt
1 = disable (mask) interrupt
6
CNTR6_INT_MSK
1
Counter 6 Interrupt Mask—blocks (masks) the interrupt for
counter 6.
0 = enable interrupt
1 = disable (mask) interrupt
5
CNTR5_INT_MSK
1
Counter 5 Interrupt Mask—blocks (masks) the interrupt for
counter 5.
0 = enable interrupt
1 = disable (mask) interrupt
4
CNTR4_INT_MSK
1
Counter 4 Interrupt Mask—blocks (masks) the interrupt for
counter 4.
0 = enable interrupt
1 = disable (mask) interrupt
3
CNTR3_INT_MSK
1
Counter 3 Interrupt Mask—blocks (masks) the interrupt for
counter 3.
0 = enable interrupt
1 = disable (mask) interrupt
2
CNTR2_INT_MSK
1
Counter 2 Interrupt Mask—blocks (masks) the interrupt for
counter 2.
0 = enable interrupt
1 = disable (mask) interrupt
1
CNTR1_INT_MSK
1
Counter 1 Interrupt Mask—blocks (masks) the interrupt for
counter 1.
0 = enable interrupt
1 = disable (mask) interrupt
0
CNTR0_INT_MSK
1
Counter 0 Interrupt Mask—blocks (masks) the interrupt for
counter 0.
0 = enable interrupt
1 = disable (mask) interrupt
Address offset:
0x58
Access:
Read/clear
Bits
Field
Default
Description
15
CNTR15_INT_STAT
-
Counter 15 Interrupt Status—provides current interrupt status
for counter 15.
0 = interrupt is de-asserted
1 = interrupt is asserted
14
CNTR14_INT_STAT
-
Counter 14 Interrupt Status—provides current interrupt status
for counter 14.
0 = interrupt is de-asserted
1 = interrupt is asserted
Bits
Field
Default
Description
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com