C2K User’s Guide
5-46
Resources
5.2.6 Standard USART Registers
Table 5-12 lists the standard 16550-compatible USART registers. The offset is from the base
address of each USART.
USART Receive Buffer Register
The USART Receive Buffer Register holds the incoming receive data after it has been transferred
from the incoming shift register. In FIFO mode, this register contains a receive-data byte pulled
from the top of the memory buffer.
3 - 2
FIFO_SIZE
0b00
FIFO Size—selects the transmit and receive data FIFO
buffer size.
0b00 = 16 bytes
0b01 = 64 bytes
0b10 = 256 bytes
0b11 = 1024 bytes
1
TXCLK_SRC
0
Transmit Clock Source—selects the source of the trans-
mit clock in synchronous mode.
0 = internal baud-rate generator
1 = receive clock
0
SYNC
0
Synchronization Mode—selects the synchronization
mode in which USART will operate.
0 = standard asynchronous mode
1 = external clock synchronous mode
Table 5-12
Standard 16550-compatible USART registers
Offset
DLAB
Register
Description
0x0
0
Receive Buffer
Transmit Buffer
Receive data buffer (read).
Transmit data buffer (write).
0x1
0
Interrupt Enable
Interrupt event enable/mask.
0x2
X
Interrupt Identification
FIFO Control
Interrupt event status (read).
FIFO control settings (write).
0x3
X
Line Control
Line control settings.
0x4
X
Modem Control
Modem control settings.
0x5
X
Line Status
Line status indications.
0x6
X
Modem Status
Modem status indications.
0x7
X
Scratchpad
Scratchpad data.
0x0
1
Divisor Latch (LSB)
Least-significant byte of baud-rate divisor.
0x1
1
Divisor Latch (MSB)
Most-significant byte of baud-rate divisor.
Address offset:
USAR0x0
DLAB:
0
Access:
Read-only
Bits
Field
Default
Description
7 - 0
RXDATA
0x00
Receive buffer data
Bits
Field
Default
Description
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