Furuno FM-8800, Руководство по обслуживанию, Страница: 196 / 268

8.3 T/A, TEST, RESET DSP
8-16
5. DUP RX
5.1 PLL
This adjusts the PLL circuit on DUP RX board. Frequency selected is set up as
DUP RX PLL frequency data.
** DUP RX PLL **
１
55.00 MHz
160.00 MHz
165.00 MHz
5.2 AGC
This is not in use. This is only equipped in case checking AGC functions with
“CHANNEL” knob or [
▲
] [
▼
] key. The voltage of J10-#25 and J8-#12(AGC
CONT) on CPU board will be changed by this adjustment.
AGC Test out
1.10V – 3.65V
<
■■
> 1.65
EXT : EXT
6. DDS/CODEC
This is a test for DDS: U25 and CODEC: U17 and U10 on CPU board. This is a
loop-back test where test signal is transmitted from U17 and is detected by U10. Output
signal transmitted from U17 is a sine wave of 2 kHz. The signal will be assessed “OK”
if U10 detects this frequency and a designated level. “P” indicates the percentage of
frequency of 2 kHz and “A” indicates the amplitude of RX signal. This test is carried
out and assessed just the same as CPU PCB self-test is which is explained in Self-test
section. DDS check is carried out just as mentioned above and test signal is transmitted
from DDS.
*** DDS/CODEC TEST ***
DDS
P : 100 A : 19653
4528 L P : 100 A : 19960
4528 R P : 100 A : 19801
RX: 1st Lo frequency
Fo + 51.2375 MHz
Judgment value to be OK
P A
DDS More than 20 More than 6000
4528 L More than 90 More than 6000
4528 R More than 90 More than 6000