PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
8
Freescale Semiconductor
Clocking
3.2
Clocking Example
Let us assume that we want to maximize the frequencies of certain key interfaces. We can use the following
inputs:
•
SYSCLK = 66 MHz
•
CCB multiplier = 5 (cfg_sys_pll)
•
Core multiplier = 2.5 (cfg_core_pll)
•
Local bus divider = 2 (LCRR[CLKDIV])
The resulting frequencies for the following interfaces are:
•
Core = SYSCLK * cfg_sys_pll * cfg_core_pll = 833 MHz
•
CPM = SYSCLK * cfg_sys_pll = 333 MHz
•
DDR (MCKn) = SYSCLK * cfg_sys_pll/2 = 167MHz = 333 MHz data rate
•
PCI = SYSCLK = 66 MHz
•
Local Bus (LCLKn) = SYSCLK * cfg_sys_pll / CLKLDIV = 167 MHz
These are the current maximum frequencies. Check the relevant product web site for updated options.
3.3
Core Clock
The frequency of the core is determined at POR through the LALE and the LGPL2 pins. Below are the
options for configuring the core clock as a multiple of the CCB clock. This information can be found in
the
MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual
(MPC8555ERM).
3.4
DDR SDRAM Clock Outputs
The DDR SDRAM clock outputs MCK[0:5] and MCK[0:5] are derived from the CCB clock. No
configuration pins or register settings are required to generate the MCK/MCKn frequencies because they
are by default one-half the CCB clock frequency.
PCI1, PCI2
SYSCLK, or PCI_CLK
TSEC
125MHz from PHY or External (certain modes)
Table 4. Core Clock POR Configuration
LALE, LGPL2
Core: CCB
00
2:1
01
5:2 (2.5:1)
10
3:1
11
7:2 (3.5:1)
Table 3. Clocking Quick Reference (continued)
Functional Block
Clock Derivation