Freescale Semiconductor PowerQUICC III MPC8541E Скачать руководство пользователя страница 17 | Manualshive

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Freescale Semiconductor PowerQUICC III MPC8541E Скачать руководство пользователя страница 17

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

Freescale Semiconductor

17

Functional Blocks

6.2

Core

Multiprocessor functionality is not implemented in the PowerQUICC III e500 core:

•

There are no shared (S) states in the L1 or L2 cache.

•

The memory coherence bit, M, controlled through MAS2[M] / MAS4[MD] and MAS2[SHAREN]
/MAS4[SHAREND], has no effect.

•

HID1[MSHARS] and HID1[SSHAR] are not implemented.

•

HID1[ABE] is only used to ensure (when set) that cache and TLB management instructions operate
properly with respect to the L2 cache.

•

There is no dynamic bus snooping. If the PowerQUICC III is in a nap or sleep state, then the core
is not wakened to snoop global transactions.

The PowerQUICC III does not implement a double-precision floating point. If this is needed, it can be
emulated through software. The PowerQUICC III supports single-precision scalar and single-precision
vector floating point only through various APUs on-chip. In addition, 64-bit operands are not supported
because the e500 is a 32-bit implementation of Book-E.

The SPE, and SPFP APUs functionality will not be implemented in the next generation of PowerQUICC
devices. Freescale strongly recommends that use of these instructions be confined to libraries and device
drivers. Customer software that uses SPE or SPFP APU instructions at the assembly level or that uses SPE
intrinsics will require rewriting for upward compatibility with next generation PowerQUICC devices.
Freescale offers a lib_moto_e500 library that uses SPE and SPFP APU instructions. Freescale will also
provide future libraries to support next generation PowerQUICC devices.

6.3

DDR SDRAM

Please refer to the following application notes for detailed information on layout consideration and DDR
programming guidelines:

•

AN2582

: Hardware and Layout Design Considerations for DDR Memory Interfaces

for details on

signal integrity and layout considerations.

•

AN2583

: Programming the PowerQUICC III™ DDR SDRAM Controller

on DDR programming

guidelines.

The DDR bus should not be configured during use. Rather, it should be configured by executing code from
another interface (i.e., Local Bus).

NOTE

•

In the DDR controller of the MPC8555E and MPC8541, only the source
synchronous mode is supported. For proper operation, the external
signals MSYNC_IN and MSYNC_OUT should be connected to each
other.

•

The source synchronous mode bit field must be set during initilization:
DDR_SDRAM_CLK_CNTL[SS_EN] = 1

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Содержание PowerQUICC III MPC8541E

Страница 1: ...he aspects of a design that merit special attention during initial system startup 1 Getting Started This section outlines recommendations to simplify the first phase of design Before designing a syste...

Страница 2: ...e respective PowerQUICC III device 1 3 Communications Processor Module CPM Performance and Bus Utilization Tool The PowerQUICC III CPM runs by time sharing multiple communication protocols To estimate...

Страница 3: ...Tool is available on the MPC8555E or MPC8541E device web site 1 7 Available Training Our third party partners are part of an extensive Design Alliance Program Our current training partners are listed...

Страница 4: ...supply the type of load on each power supply and the way different voltages are derived The MPC8555E and MPC8541E require the power rails to be applied in a specific sequence to ensure proper device o...

Страница 5: ...ponents in the PowerQUICC III system and the PowerQUICC III itself requires a clean tightly regulated source of power Therefore you should place at least one decoupling capacitor at each VDD GVDD LVDD...

Страница 6: ...from the capacitors to the AVDD pin which is on the periphery of the 783 FC PBGA footprint without the inductance of vias If possible a separate plane for each PLL filtering circuit is recommended 3 C...

Страница 7: ...ion Core including L1 CCB 2 2 5 3 3 5 DDR CCB 2 I2 C CCB I2CFDR ratio L2 cache CPM CCB Local Bus CCB 2 4 8 Core PLL Platform PLL DLL LSYNC_IN LSYNC_OUT LCLK0 LCLK1 core_clk e500 Core CCB_clk to Rest o...

Страница 8: ...nt product web site for updated options 3 3 Core Clock The frequency of the core is determined at POR through the LALE and the LGPL2 pins Below are the options for configuring the core clock as a mult...

Страница 9: ...terfaces on the MPC8555E and the MPC8541E is by default the system clock SYSCLK input In asynchronous mode each PCI PCI1 PCI2 interface can be configured to use a separate PCI clock input unrelated to...

Страница 10: ...4 1 TRST TRST is the reset pin for the JTAG COP interface It must be held at a low level during the assertion of HRESET to reset all logic completely on the PowerQUICC III For compatibility with thir...

Страница 11: ...Connector Physical Pinout 1 2 NC SRESET 2 Populate this with a 10 resistor for short circuit current limiting protection NC OVDD 10 k 10 k HRESET1 to fully control the processor as shown here 4 Altho...

Страница 12: ...o that it is asserted when the system reset signal HRESET is asserted ensuring that the JTAG scan chain is initialized during Table 6 COP Header Definition Header Position Name Description 1 COP_TDO T...

Страница 13: ...rally output pins during normal operation they are treated as inputs while HRESET is asserted HRESET must be asserted for a minimum of 100 s When HRESET negates the configuration pins are sampled and...

Страница 14: ...ins LAD 0 31 to software For example we can pass information about a circuit board revision number to software by driving the pins in any order The information is automatically sampled from LAD 0 31 d...

Страница 15: ...41EEC 5 3 Boot Sequencer The boot sequencer allows configuration of any memory mapped register before the boot up code runs When enabled it loads code from an EEPROM on the I2C bus This code can be us...

Страница 16: ...are not used it would be more power efficient to disable these interfaces The device disable register DEVDISR contains disable bits for the PCI1 PCI2 LBC SEC L2 DDR e500 Time Base CPM DMA TSEC1 TSEC2...

Страница 17: ...neration of PowerQUICC devices Freescale strongly recommends that use of these instructions be confined to libraries and device drivers Customer software that uses SPE or SPFP APU instructions at the...

Страница 18: ...s high through a resistor Recommended resistor values are 2 10 k 6 5 Local Bus Interface Unit The local bus frequency can be adjusted through the LCRR CLKDIV bit If modified the DLL requires a re lock...

Страница 19: ...K 6 5 3 Timing Local bus output valid hold and tri state timings can be adjusted at reset by the POR pins TSEC2_TXD 6 5 These pins directly affect local bus AC timing by adding up to three buffer del...

Страница 20: ...hese internal pull ups are not enabled in 64 bit mode If there is concern that in 32 bit mode these inputs may see noise that would cause unwanted power consumption then external pull up resistors can...

Страница 21: ...of the device pins Instead the PCI CLK is realized on the SYSCLK input and the PCI RST is realized on the HRESET input 6 7 Three Speed Ethernet Controller TSEC The TSEC has one management interface th...

Страница 22: ...en 2 10 K In general inputs can be tied together to a single resistor I Os must be tied off with a single resistor per I O except on the PCI interface see Section 6 6 PCI Note that if you are not usin...

Страница 23: ...ied Section 2 3 Power Sequencing Modified signal names in Table 6 2 6 2006 Updates are as follows Modified note in Section 6 3 DDR SDRAM to clarify that while MSYNC_IN mube connected to MSYNC_OUT the...

Страница 24: ...and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any lic...

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