Freescale Semiconductor PowerQUICC III MPC8541E Скачать руководство пользователя страница 20 | Manualshive

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Freescale Semiconductor PowerQUICC III MPC8541E Скачать руководство пользователя страница 20

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

20

Freescale Semiconductor

Functional Blocks

For address latch hold time t

LBOTOT

, the LBCR[AHD] bit is used to further adjust t

LBOTOT

. It removes

part of the hold time for LAD with respect to LALE to lengthen the LALE pulse. It can remove either a
half or a full CCB clock period.

shows how t

LBOTOT

is programmed.

6.6

PCI

6.6.1

Termination of Signals during Normal Operation

You should verify signal integrity by simulating with the current IBIS model. For standard operation of the
PCI port, pull-ups are necessary to guarantee the state of control signals when no agent is driving the bus.
The

PCI Local Bus Specification

requires a pull-up on the PCI1_FRAME, PCI1_TRDY, PCI1_IRDY,

PCI2_TRDY, PCI2_IRDY, PCI1_DEVSEL, PCI1_STOP, PCI1_SERR, PCI1_PERR, PCI2_STOP,
PCI2_SERR, PCI2_PERR,PCI1_REQ64, and PCI1_ACK64 pins. Weak pull-ups of 2–10 K

Ω

are

recommended for these pins.

When in 32-bit PCI mode, the PowerQUICC III enables weak internal pull-ups on PCI1_AD[63:32],
PCI_C_BE[7:4], and PCI1_PAR64. These internal pull-ups are not enabled in 64-bit mode. If there is
concern that in 32-bit mode these inputs may see noise that would cause unwanted power consumption,
then external pull-up resistors can be placed on them to further guarantee their logic-one state when in
32-bit mode.

The PCI1_REQ64 pin functionally requires a pull-up resistor per the

PCI Local Bus Specification

;

however, during reset it is a configuration input for PowerQUICC III that determines 32- or 64-bit PCI
operation. If the PowerQUICC III is to be configured as a 64-bit PCI device, it must be actively driven low
during reset by reset logic. Because PowerQUICC III does not implement an override to this specified
protocol for selecting 64-bit operation, the signal would have to be driven low with a tri-stateable driver
or similar logic during reset and then released to select 64-bit PCI operation.

If the PowerQUICC III is the host that initiates PCI transactions, you should pull the IDSEL pin low to
guard against the PowerQUICC III replying to one of its own bus transactions.

Table 9. Programming t

LBOTOT

LBCR[AHD]

TSEC2_TXD[6:5]

t

LBOTOT

0

00

CCBCLK

0

01

3BDs

0

10

2BDs

0

11

1BD

1

00

CCBCLK/2

1

01

CCBCLK/2 + 3BDs

1

10

CCBCLK/2 + 2BDs

1

11

CCBCLK/2 + 1BD

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Содержание PowerQUICC III MPC8541E

Страница 1: ...he aspects of a design that merit special attention during initial system startup 1 Getting Started This section outlines recommendations to simplify the first phase of design Before designing a syste...

Страница 2: ...e respective PowerQUICC III device 1 3 Communications Processor Module CPM Performance and Bus Utilization Tool The PowerQUICC III CPM runs by time sharing multiple communication protocols To estimate...

Страница 3: ...Tool is available on the MPC8555E or MPC8541E device web site 1 7 Available Training Our third party partners are part of an extensive Design Alliance Program Our current training partners are listed...

Страница 4: ...supply the type of load on each power supply and the way different voltages are derived The MPC8555E and MPC8541E require the power rails to be applied in a specific sequence to ensure proper device o...

Страница 5: ...ponents in the PowerQUICC III system and the PowerQUICC III itself requires a clean tightly regulated source of power Therefore you should place at least one decoupling capacitor at each VDD GVDD LVDD...

Страница 6: ...from the capacitors to the AVDD pin which is on the periphery of the 783 FC PBGA footprint without the inductance of vias If possible a separate plane for each PLL filtering circuit is recommended 3 C...

Страница 7: ...ion Core including L1 CCB 2 2 5 3 3 5 DDR CCB 2 I2 C CCB I2CFDR ratio L2 cache CPM CCB Local Bus CCB 2 4 8 Core PLL Platform PLL DLL LSYNC_IN LSYNC_OUT LCLK0 LCLK1 core_clk e500 Core CCB_clk to Rest o...

Страница 8: ...nt product web site for updated options 3 3 Core Clock The frequency of the core is determined at POR through the LALE and the LGPL2 pins Below are the options for configuring the core clock as a mult...

Страница 9: ...terfaces on the MPC8555E and the MPC8541E is by default the system clock SYSCLK input In asynchronous mode each PCI PCI1 PCI2 interface can be configured to use a separate PCI clock input unrelated to...

Страница 10: ...4 1 TRST TRST is the reset pin for the JTAG COP interface It must be held at a low level during the assertion of HRESET to reset all logic completely on the PowerQUICC III For compatibility with thir...

Страница 11: ...Connector Physical Pinout 1 2 NC SRESET 2 Populate this with a 10 resistor for short circuit current limiting protection NC OVDD 10 k 10 k HRESET1 to fully control the processor as shown here 4 Altho...

Страница 12: ...o that it is asserted when the system reset signal HRESET is asserted ensuring that the JTAG scan chain is initialized during Table 6 COP Header Definition Header Position Name Description 1 COP_TDO T...

Страница 13: ...rally output pins during normal operation they are treated as inputs while HRESET is asserted HRESET must be asserted for a minimum of 100 s When HRESET negates the configuration pins are sampled and...

Страница 14: ...ins LAD 0 31 to software For example we can pass information about a circuit board revision number to software by driving the pins in any order The information is automatically sampled from LAD 0 31 d...

Страница 15: ...41EEC 5 3 Boot Sequencer The boot sequencer allows configuration of any memory mapped register before the boot up code runs When enabled it loads code from an EEPROM on the I2C bus This code can be us...

Страница 16: ...are not used it would be more power efficient to disable these interfaces The device disable register DEVDISR contains disable bits for the PCI1 PCI2 LBC SEC L2 DDR e500 Time Base CPM DMA TSEC1 TSEC2...

Страница 17: ...neration of PowerQUICC devices Freescale strongly recommends that use of these instructions be confined to libraries and device drivers Customer software that uses SPE or SPFP APU instructions at the...

Страница 18: ...s high through a resistor Recommended resistor values are 2 10 k 6 5 Local Bus Interface Unit The local bus frequency can be adjusted through the LCRR CLKDIV bit If modified the DLL requires a re lock...

Страница 19: ...K 6 5 3 Timing Local bus output valid hold and tri state timings can be adjusted at reset by the POR pins TSEC2_TXD 6 5 These pins directly affect local bus AC timing by adding up to three buffer del...

Страница 20: ...hese internal pull ups are not enabled in 64 bit mode If there is concern that in 32 bit mode these inputs may see noise that would cause unwanted power consumption then external pull up resistors can...

Страница 21: ...of the device pins Instead the PCI CLK is realized on the SYSCLK input and the PCI RST is realized on the HRESET input 6 7 Three Speed Ethernet Controller TSEC The TSEC has one management interface th...

Страница 22: ...en 2 10 K In general inputs can be tied together to a single resistor I Os must be tied off with a single resistor per I O except on the PCI interface see Section 6 6 PCI Note that if you are not usin...

Страница 23: ...ied Section 2 3 Power Sequencing Modified signal names in Table 6 2 6 2006 Updates are as follows Modified note in Section 6 3 DDR SDRAM to clarify that while MSYNC_IN mube connected to MSYNC_OUT the...

Страница 24: ...and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any lic...

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