manualshive.com logo in svg

Freescale Semiconductor PowerQUICC III MPC8541E, Руководство пользователя, Страница: 14 / 24

Поделиться
Скачать
Freescale Semiconductor PowerQUICC III MPC8541E Скачать руководство пользователя страница 14

PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5

14

Freescale Semiconductor

 

Power-On Reset/Reset Configurations

An alternative to pull-up and pull-down resistors to configure the POR pins is to use a PLD, DIP switch, 
or similar device to drive the configuration signals when HRESET is asserted. The PLD must begin to 
drive these signals at least four SYSCLK cycles prior to the negation of HRESET (PLL configuration 
inputs must meet a 100 ms set-up time to HRESET), hold their values for at least 2 SYSCLK cycles after 
the negation of HRESET, and tri-state the pins afterwards for normal device operation. For details on the 
power-on reset configurations and their definitions, refer to the 

MPC8555E/MPC8541E PowerQUICC™ 

III Integrated Communications Processor Reference Manual

 (MPC8555ERM).

5.1

Useful System POR Debug Registers

The POR configuration settings can be read in the POR PLL status register (PORPLLSR), the POR boot 
mode status register (PORBMSR), the POR I/O impedance status and control register (PORIMPSCR), the 
POR device status register (PORDEVSR), the POR debug mode status register (PODBGMSR), and the 
general-purpose POR configuration register (GPPORCR). See the MPC8555ERM for details on these 
registers, which are all read-only registers except for PORIMPSCR.

GPPORCR can be used to pass any information on the local bus address/data pins LAD[0:31] to software. 
For example, we can pass information about a circuit board revision number to software by driving the 
pins in any order. The information is automatically sampled from LAD[0:31] during POR. Then software 

TSEC1 Protocol

TSEC2_TXD[3]

TSEC1 operates using the TBI (or RTBI) protocol

TSEC2 Protocol

TSEC2_TXD[2]

TSEC2 operates using the TBI (or RTBI) protocol

PCI1 Clock Select

TSEC2_TXD[1]

SYSCLK is used as default clock for PCI1

PCI2 Clock Select

TSEC2_TXD[0]

SYSCLK is used as default clock for PCI2

PCI 32bit configuration

PCI2_FRAME

PCI interface operates as two 32-bit interface

PCI1 I/O Impedance

PCI1_GNT1

42

Ω

 drivers are used on the PCI1 interface

PCI2 I/O Impedance

PCI2_GNT1

42

Ω

 drivers are used on the PCI1 interface

PCI1 Arbiter 

PCI1_GNT2

PCI1 Arbiter enabled

PCI2 Arbiter

PCI2_GNT2

PCI2 Arbiter enabled

PCI Debug

PCI1_GNT3

PCI operates in normal mode

Memory Debug

MSRCID0

DDR debug information is driven on MSRCID and MDVAL

DDR Debug

MSRCID1

No debug information is driven on the ECC pins

PCI1 Output Hold

PCI1_GNT4

PCI1: Two added buffer delays to meet 2ns hold time
(In 64bit PCI mode applies to lower 32bit)

PCI2 Output Hold

PCI2_GNT4

PCI2: Two added buffer delays to meet 2ns hold time
(In 64bit PCI mode applies to upper 32bit)

Local Bus Output Hold

LWE[0:1]

One added buffer delay

General Purpose POR

LAD[0:31]

No default state; pins must be configured at HRESET if GPPORCR is 
intended to be accessed by a user system

Table 7. Power-On Reset Configurations (continued)

Type of Configuration

Configuration Pins

Default State

Содержание PowerQUICC III MPC8541E

Страница 1: ...he aspects of a design that merit special attention during initial system startup 1 Getting Started This section outlines recommendations to simplify the first phase of design Before designing a syste...

Страница 2: ...e respective PowerQUICC III device 1 3 Communications Processor Module CPM Performance and Bus Utilization Tool The PowerQUICC III CPM runs by time sharing multiple communication protocols To estimate...

Страница 3: ...Tool is available on the MPC8555E or MPC8541E device web site 1 7 Available Training Our third party partners are part of an extensive Design Alliance Program Our current training partners are listed...

Страница 4: ...supply the type of load on each power supply and the way different voltages are derived The MPC8555E and MPC8541E require the power rails to be applied in a specific sequence to ensure proper device o...

Страница 5: ...ponents in the PowerQUICC III system and the PowerQUICC III itself requires a clean tightly regulated source of power Therefore you should place at least one decoupling capacitor at each VDD GVDD LVDD...

Страница 6: ...from the capacitors to the AVDD pin which is on the periphery of the 783 FC PBGA footprint without the inductance of vias If possible a separate plane for each PLL filtering circuit is recommended 3 C...

Страница 7: ...ion Core including L1 CCB 2 2 5 3 3 5 DDR CCB 2 I2 C CCB I2CFDR ratio L2 cache CPM CCB Local Bus CCB 2 4 8 Core PLL Platform PLL DLL LSYNC_IN LSYNC_OUT LCLK0 LCLK1 core_clk e500 Core CCB_clk to Rest o...

Страница 8: ...nt product web site for updated options 3 3 Core Clock The frequency of the core is determined at POR through the LALE and the LGPL2 pins Below are the options for configuring the core clock as a mult...

Страница 9: ...terfaces on the MPC8555E and the MPC8541E is by default the system clock SYSCLK input In asynchronous mode each PCI PCI1 PCI2 interface can be configured to use a separate PCI clock input unrelated to...

Страница 10: ...4 1 TRST TRST is the reset pin for the JTAG COP interface It must be held at a low level during the assertion of HRESET to reset all logic completely on the PowerQUICC III For compatibility with thir...

Страница 11: ...Connector Physical Pinout 1 2 NC SRESET 2 Populate this with a 10 resistor for short circuit current limiting protection NC OVDD 10 k 10 k HRESET1 to fully control the processor as shown here 4 Altho...

Страница 12: ...o that it is asserted when the system reset signal HRESET is asserted ensuring that the JTAG scan chain is initialized during Table 6 COP Header Definition Header Position Name Description 1 COP_TDO T...

Страница 13: ...rally output pins during normal operation they are treated as inputs while HRESET is asserted HRESET must be asserted for a minimum of 100 s When HRESET negates the configuration pins are sampled and...

Страница 14: ...ins LAD 0 31 to software For example we can pass information about a circuit board revision number to software by driving the pins in any order The information is automatically sampled from LAD 0 31 d...

Страница 15: ...41EEC 5 3 Boot Sequencer The boot sequencer allows configuration of any memory mapped register before the boot up code runs When enabled it loads code from an EEPROM on the I2C bus This code can be us...

Страница 16: ...are not used it would be more power efficient to disable these interfaces The device disable register DEVDISR contains disable bits for the PCI1 PCI2 LBC SEC L2 DDR e500 Time Base CPM DMA TSEC1 TSEC2...

Страница 17: ...neration of PowerQUICC devices Freescale strongly recommends that use of these instructions be confined to libraries and device drivers Customer software that uses SPE or SPFP APU instructions at the...

Страница 18: ...s high through a resistor Recommended resistor values are 2 10 k 6 5 Local Bus Interface Unit The local bus frequency can be adjusted through the LCRR CLKDIV bit If modified the DLL requires a re lock...

Страница 19: ...K 6 5 3 Timing Local bus output valid hold and tri state timings can be adjusted at reset by the POR pins TSEC2_TXD 6 5 These pins directly affect local bus AC timing by adding up to three buffer del...

Страница 20: ...hese internal pull ups are not enabled in 64 bit mode If there is concern that in 32 bit mode these inputs may see noise that would cause unwanted power consumption then external pull up resistors can...

Страница 21: ...of the device pins Instead the PCI CLK is realized on the SYSCLK input and the PCI RST is realized on the HRESET input 6 7 Three Speed Ethernet Controller TSEC The TSEC has one management interface th...

Страница 22: ...en 2 10 K In general inputs can be tied together to a single resistor I Os must be tied off with a single resistor per I O except on the PCI interface see Section 6 6 PCI Note that if you are not usin...

Страница 23: ...ied Section 2 3 Power Sequencing Modified signal names in Table 6 2 6 2006 Updates are as follows Modified note in Section 6 3 DDR SDRAM to clarify that while MSYNC_IN mube connected to MSYNC_OUT the...

Страница 24: ...and actual performance may vary over time All operating parameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any lic...

Отзывы:

Нет отзывов