Freescale Semiconductor PowerPC e500 Core, Справочное руководство

Страница: 428 / 548

PowerPC e500 Core Family Reference Manual, Rev. 1
13-6 Freescale Semiconductor
Core Complex Bus (CCB)
(burst write) operation from the core complex MCSR[DCP_PERR] is set. A front-side L2 does
not cache the bad data. The system has enough information to prevent memory corruption.
The address attribute signal, wt, is also asserted during the address tenure for that transaction. By
setting L1CSR0[CPE], the core complex may be configured to also take a data cache parity error
exception.
Parity error handling is described in Section 5.7.2, “Machine Check Interrupt .”
13.3.2 msync Operation and the Bus
The msync instruction provides a synchronization boundary for instruction execution. Its
architectural intent is to guarantee that the effects of all instructions prior to the msync instruction
have occurred before any subsequent instructions begin execution. It may be used, for example, to
ensure that a control bit has finally been written to its destination control register in the system
before the next instruction begins execution (such as to clear a pending interrupt). By its nature, it
also provides an ordering boundary for pre- and post-msync memory transactions.
For the core complex, an msync does not finish execution until all memory transactions caused by
prior instructions complete entirely in its caches and externally on the bus (address and data
transactions complete, excluding instruction fetches). No subsequent instructions and associated
memory transactions are initiated until such completion occurs. Execution of msync also
generates a SYNC command on the bus (if HID1[ABE] is set through the tt[0:4] signals), which
also must complete normally (without address retry) for the msync instruction to complete.
13.3.3 mbar Operation and the Bus
The mbar instruction provides an ordering boundary for memory operations. Its architectural
intent is to guarantee that memory operations resulting from instructions prior to the mbar
instruction occur before any subsequent memory operations occur (thereby ensuring an order
between pre- and post-mbar memory operations). It may be used, for example, to ensure that reads
and writes to an I/O device or between I/O devices occur in program order, or to ensure that
memory updates occur before a semaphore is released.
The Book E architecture allows an implementation to support several classes of memory ordering,
selected by the MO field of the mbar instruction. The core complex supports two classes for
system flexibility. For MO
≥
0, the core complex re-interprets and executes mbar as an msync,
which by its nature guarantees an order between all pre- and post-mbar memory transactions.
For MO = 1, the core complex executes the mbar instruction as a pipelined or flowing ordering
barrier for potentially higher performance. For this case, an ordering barrier is established by the
mbar instruction and flows along with the pre- and post-mbar memory transactions through the
memory hierarchy (L1 cache, bus, and system). On the bus, this ordering barrier is issued as an
ORDER command (if HID1[ABE] is set through tt[0:4]).