Freescale Semiconductor PowerPC e500 Core, Справочное руководство

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Core Complex Bus (CCB)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 13-5
13.3 Core Interface Behavior
This section describes the behavior of the core interface with respect to parity and the
synchronizing instructions, mbar and msync.
13.3.1 Parity Specification
The CCB supports byte parity (odd parity) on each data bus. Parity checking for the read data
buses is enabled by setting HID1[R1DPE,R2DPE].
For write transactions, the core complex always supplies correct data parity across all byte lanes
of the write data bus. If an internal parity error is detected in the L1 data cache during a castout
core_fault_in I Core bus fault input. When asserted, signals a bus fault. On the e500v2, prevents the core transaction from
completing, protecting the code from executing with potentially bad data. Thus, the transaction stalls waiting
for an interrupt. If HID1[RFXE] = 1 and MSR[ME] = 1, assertion of
core_fault_in causes a machine check
interrupt and if HID1[RFXE] = 1 and MSR[ME] = 0, it causes a checkstop. For more information about bus
faults, see
Section 13.8, “Proper Reporting of Bus Faults .” For proper handling of bus faults, see
Section 2.10.2, “Hardware Implementation-Dependent Register 1 (HID1) .”
Power Management Signals for the Core Complex
halt I Asserted by system logic to request the core complex to go into halted state. Negating halt causes the core
complex to transition back into the full-on state. Once asserted, halt must not be negated until after the core
complex has entered halted state (otherwise the negation may not be recognized).
stop I Asserted by system logic to request that the core complex go from the halted state into the power-down state.
Negating this signal causes the core complex to transition back into the halted state. Once asserted,
stop must
not be negated until after the core complex has entered the stopped state (otherwise the negation may not be
recognized). For power management purposes,
stop must be asserted only while the core complex is in halted
state.
halted O Asserted when the core complex is in the halted state. It is the indication that it is safe for e500 core to go into
the power-down state.
stopped O Asserted any time the internal functional clocks of the core complex are stopped.
doze O Reflect the state of the corresponding HID0 DOZE, NAP, and SLEEP bits, further qualified with MSR[WE] = 1
(both must be 1 for the respective output to be asserted). The state of these signals has no effect on the
power-down state of the core complex. They serve only as indicators to external logic of power management
requests by software.
nap O
sleep O
Miscellaneous Signals
pm_event I External event. A level-sensitive input to e500 performance monitor to count external events.
pvr [0:31] O Processor version. The processor version information is provided for reading through a system SPR. Static
signals during functional mode.
svr [0:31]
I System version. The system version information is directly readable through an SPR in the core complex.
Static signals during functional mode.
Table 13-1. Summary of Selected Internal Signals (continued)
Signal I/O Comments, or Meaning when Asserted