Freescale Semiconductor PowerPC e500 Core, Справочное руководство

Страница: 385 / 548

L1 Caches
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 11-23
11.6.1 Cache Miss and Reload Operations
This section describes the actions taken by the L1 caches on misses for caching-allowed accesses.
It also describes what happens on cache misses for caching-inhibited accesses as well as disabled
and locked L1 cache conditions.
11.6.1.1 Data Cache Fills
The core complex data cache blocks are filled (sometimes referred to as a cache reload) from an
L2 cache or the memory subsystem when cache misses occur for caching-allowed accesses, as
described in
Section 11.1.1.1, “Load/Store Unit (LSU) ,” and Section 11.1.1.2, “Instruction Unit .”
When the data cache is disabled (L1CSR0[CE] = 0), data accesses bypass the data cache, are
forwarded to the memory subsystem as caching-allowed, and proceed to the CCB. Returned data
is forwarded to the requesting execution unit, but is not loaded into any of the caches.
Each of the eight ways of each set in the data cache can be locked (by locking all of the cache lines
in the way with the dcbtls or dcbtstls instruction). When at least one way is unlocked, misses are
treated normally and are allocated to one of the unlocked ways on a reload. If all eight ways are
locked, store/load misses proceed to the memory subsystem as normal caching-allowed accesses.
In this case, the data is forwarded to the requesting execution unit when it returns, but it is not
loaded into the data cache. If the data is modified, it is loaded into a DWB and creates the
appropriate normal burst write transfer.
Each of the eight ways of each set in the instruction cache can be locked (by locking all of the
cache lines in the way with the icbtls instruction). When at least one way is unlocked, misses are
treated normally and they are allocated to one of the unlocked ways on a reload. If all of the ways
are locked, instruction misses proceed to the memory subsystem as normal caching-allowed
accesses. In this case, the instruction is forwarded to the instruction unit when it returns, but it is
not loaded into the instruction cache.
Note that caching-inhibited stores should not access any of the caches (see Section 11.3.4.3,
“Caching-Inhibited Loads and Stores ,” for more information). See Section 11.6.1.4, “Store Miss
Merging ,” for more information on the handling of caching-allowed store misses.
11.6.1.2 Instruction Cache Fills
The instruction cache provides a 128-bit interface to the instruction unit, so as many as four
instructions can be made available to the instruction unit in a single clock cycle on an L1
instruction cache hit. On a miss, the core complex instruction cache blocks are loaded in one
32-byte beat from the CCB; the instruction cache is nonblocking, providing for hits under misses.
The instruction cache operates similarly to the data cache when all eight ways of a set are locked.
When the instruction cache is disabled (L1CSR1[ICE] = 0), instruction accesses bypass the
instruction cache. These accesses are forwarded to the memory subsystem as caching-allowed and