ATA Interface
MPC5200 ATA Interface, Rev. 0
Freescale Semiconductor
9
The following steps should be used to set up the cache for ATA memory buffer regions:
•
Set DBAT registers and enable data cache.
2
(See
Programming Environments Manual for 32-Bit
Implementations of the PowerPC Architecture
for details.)
•
Set XLB priorities in the XLB arbiter master priority register and enable XLB priorities in the
arbiter master priority enable register.
3
(See the XLB Arbiter chapter in the
MPC5200 User’s
Manual
for details.)
•
Set window address, size and snooping policy in the XLB arbiter snoop window register and
enable snooping in the XLB arbiter configuration register.
4
(See the XLB Arbiter chapter in the
MPC5200 User’s Manual
for details.)
2.8
Host Initialization
The MPC5200 ATA host initialization covers three different groups of steps:
1. ATA common initialization
— Set ATA chip select in GPS port configuration register
— Read IPBI clock speed in CDM configuration register (66 or 132 MHz) needed for timing
registers)
5
— Enable ATA clock in CDM clock enable register
— Install ATA interrupt handler and BestComm interrupt handler for MDMA/UDMA modes
— Enable ATA/BestComm interrupt
2. PIO initialization (BestComm not needed for PIO modes)
— Set PIO timing registers
— Enable drive interrupt (to pass to CPU in PIO modes) in ATA host configuration register
(IE bit)
— Enable IORDY in ATA host configuration register (for PIO-3 and above)
3. MDMA/UDMA initialization
— Set either MDMA or UDMA timing registers
2.9
Protocols
ATA commands written into the ATA drive device command register are grouped into different classes
according to the protocols. The protocols define the command execution flow. The command classes with
their associated protocols are defined in
Table 5
.
The following sections directly document the commands instead of providing a detailed general
description for each protocol. The addressing scheme and the handling of some of the commands are
usually provided in linkable libraries by operating system vendors; therefore, the following description is
2. Usually entire memory cached, initialized by bootloader
3. Initialized by bootloader
4. Set up by driver
5. Bootloader sets up IPBI clock speed, peripheral drivers should read status only
