MPC5200 ATA Interface, Rev. 0
ATA Interface
Freescale Semiconductor
2
•
PIO (from PIO-0 to PIO-4) – up to 16.7 MBytes/sec
•
Multiword DMA (from MDMA-0 to MDMA-2) – up to 16.7 MBytes/sec
•
Ultra DMA (from UDMA-0 to UDMA-2) – up to 33 MBytes/sec
MPC5200 supports 27-bit and 48-bit LBA addressing on every device.
2
ATA Interface
The MPC5200 ATA interface includes three groups of registers:
•
ATA host registers – host configuration, timing values for all modes (from PIO, MDMA, UDMA)
•
ATA FIFO registers – control ATA FIFO for DMA modes (MDMA, UDMA)
•
ATA drive registers – access to the registers physically located on the ATA drive
Figure 1
illustrates basic components of the MPC5200 ATA interface internal to the MPC5200. Data
transfer is driven either by MPC5200 core (PIO) or by the BestComm DMA engine (MDMA, UDMA).
BestComm is designed to offload the MPC5200 core and can transfer data to/from different peripherals
simultaneously. The MPC5200 ATA interface is clocked by the IPBI clock of the MPC5200 processor
(66/132 MHz). MPC5200 acts as an ATA host and can control up to two ATA devices as defined in
ATA/ATAPI-4 specification. Pin ATA_ISOLATION of the MPC5200 (not defined as a signal by
ATA/ATAPI-4 spec) connects to the transceiver’s OE pin to control the direction (high = write to drive,
low = read from drive) of the transfer.
Figure 1. ATA Architecture
BestComm
(higher priority)
IPBI
(lower priority)
Arbite
r
ATA Rx/Tx FIFO
Interface
(MDMA/UDMA)
IPBI Interface
(PIO)
AT
A H
ost Interfa
ce
MPC5200
ATA_ISOLATION
IPBI clock (66/132 MHz)
ATA 40-pin cable
ATA
Line
Drivers
3.3 V – 5 V
ATA device 0
(e.g. DVD drive)
ATA device 1
(e.g. CompactFlash)
