MPC5200 ATA Interface, Rev. 0
Performance Analysis
Freescale Semiconductor
16
Figure 4. ATA Relative Throughput Improvement
System throughput is a result of the speed of the peripheral and the final integration—typically in OSs. For
a properly defragmented ATA device, it is considered bad programming style if the MPC5200 ATA host
reads or writes only a small number of sectors per single ATA command. In this case, the ATA software
driver and its interrupt handler could consume significant amounts of core time. The ATA software driver
can block anything running with lower priority in the system (see
Table 7
).
11
In some cases in OSs, such
bad application implementation can degrade final ATA throughput by ~50% .
.
Looking at
Table 7
,
the question arises as to why the throughput improvement indicated in
Figure 4
is not
as expected. The answer is simple; it is writing/reading the same LBA address with the look-ahead/write
cache feature disabled. The time needed to read data from the interface is much smaller (microseconds)
than the average seek time (milliseconds).
Static memory allocation for the ATA software driver is recommended.
Although not described in the
MPC5200 User’s Manual,
the MPC5200 ATA interface is capable of
UDMA-4 66 MBytes/sec mode. The programming model is the same as for UDMA-2. The impact of all
the above possible performance considerations is more visible because of higher speed.
11.Reading subsequent sectors from hard disk with enabled look-ahead feature, the worst scenario for MPC5200 core load
Table 7. System Throughput
ATA Mode
Sectors Per Single
Command
Time Between Two ATA
Interrupts
UDMA-2
1
15
µ
s
4
60
µ
s
16
240
µ
s
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.000
1.000
1.455
1.833
1.923
no
rma
liz
ed throu
ghput
2.535
16 sectors per single command
8
4
UDMA-2 write
UDMA-2 read
