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Freescale Semiconductor MPC5200, Примечание к применению

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MPC5200 ATA Interface, Rev. 0

ATA Interface

Freescale Semiconductor

6

2.6

Sector Addressing

The addressing of data sectors recorded on the device's media is performed by a logical sector address. 
Two modes are supported:

•

Cylinder/head/sector addressing (CHS)

•

Logical block addressing (LBA)

The MPC5200 host system may select either CHS translation addressing or LBA addressing on a 
command-by-command basis by using the LBA bit in the ATA drive device/head register. The LBA bit 
must be set if the host uses LBA addressing mode. The MPC5200 allows 27-bit LBA addressing per 
device.

2.7

ATA Programming Model

Figure 2

 describes the typical structure and sequence of steps needed to initialize and issue ATA 

commands for MPC5200.

0x3A78

0

1

1

1

0

Drive device/head

Drive device/head

Drive LBA bits 24-27*

Drive LBA bits 24-27*

0x3A7C

0

1

1

1

1

Drive device status

Drive command

—

0

0

x

x

x

Invalid address

Invalid address

 *Mapping of registers in LBA mode

Table 4. ATA Register Address/Chip Select Decoding (continued)

Содержание MPC5200

Страница 1: ...roller is based on an e3001 core using the PowerPCTM instruction set The ATA interface is used to connect Hard disks CD ROMs DVDs Flash storage devices The MPC5200 ATA interface is fully compatible wi...

Страница 2: ...ransfer is driven either by MPC5200 core PIO or by the BestComm DMA engine MDMA UDMA BestComm is designed to offload the MPC5200 core and can transfer data to from different peripherals simultaneously...

Страница 3: ...2 0 Vdc ViL Voltage input low logical zero 0 8 Vdc VoH Voltage output high IoH 400 A logical one 2 4 Vdc VoL Voltage output low IoL 12 mA logical zero 0 5 Vdc Table 2 ATA Signals ATA Signal ATA Acron...

Страница 4: ...5 18 Device active or slave Device 1 present DASP 39 Device address bit 0 DA0 ATA_SA_0 35 Device address bit 1 DA1 ATA_SA_1 33 Device address bit 2 DA2 ATA_SA_2 36 DMA acknowledge DMACK ATA_DACK_B 29...

Страница 5: ...DD 4 DD 3 DD 2 DD 1 DD 0 First transfer Byte 1 Byte 0 Second transfer Byte 3 Byte 2 Last transfer Byte n 1 Byte n 2 Table 4 ATA Register Address Chip Select Decoding Addresses Functions MPC5200 regis...

Страница 6: ...by using the LBA bit in the ATA drive device head register The LBA bit must be set if the host uses LBA addressing mode The MPC5200 allows 27 bit LBA addressing per device 2 7 ATA Programming Model F...

Страница 7: ...start with the software examples published on the sample code CD These software examples include a set of already pre cooked BestComm tasks that handle all required peripherals via the BestComm C API...

Страница 8: ...rdized function calls ATA device e g DVD drive ATA cable MDMA UDMA data ATA data buffers ATA software driver ATA level shifters ATA host interface MPC5200 Embedded computer Peripheral FIFOs Set of pre...

Страница 9: ...le ATA clock in CDM clock enable register Install ATA interrupt handler and BestComm interrupt handler for MDMA UDMA modes Enable ATA BestComm interrupt 2 PIO initialization BestComm not needed for PI...

Страница 10: ...AD BUFFER READ MULTIPLE READ SECTOR S SMART READ DATA PIO data out command protocol CFA WRITE MULTIPLE WITHOUT ERASE CFA WRITE SECTORS WITHOUT ERASE DOWNLOAD MICROCODE SECURITY DISABLE PASSWORD SECURI...

Страница 11: ...Initialization Protocol Steps 1 Select drive according to device selection protocol in ATA ATAPI 4 spec a Wait for BSY 0 and DRQ 0 in ATA drive alternate status register b Write ATA drive device head...

Страница 12: ...tcomm In the case of Bestcomm when snooping is not used cache needs to be invalidated first 2 9 3 PIO Data Write 2 9 3 1 PIO Data Out Command Protocol Steps 1 Select drive according to device selectio...

Страница 13: ...READ in ATA drive device command register 8 If UDMA set UDMA bit UDAMA in ATA drive device command register Clear it for MDMA 9 Set Drive Interrupt bit IE in ATA drive device command register NOTE Thi...

Страница 14: ...ive device command register by writing a logical zero bits HUT FR FE IE UDAMA READ WRITE The pending ATA drive interrupt is cleared by reading of the ATA drive device sstatus register as it is specifi...

Страница 15: ...look ahead write cache etc First they need to be checked in the identify table to see if supported and then enabled by the SET FEATURES command Using IPBI 132 MHz as described above Utilizing Bestcom...

Страница 16: ...d in Figure 4 is not as expected The answer is simple it is writing reading the same LBA address with the look ahead write cache feature disabled The time needed to read data from the interface is muc...

Страница 17: ...E32B Programming Environments Manual for 32 Bit Implementations of the PowerPC Architecture www freescale com G2CORERM G2 Core Reference Manual www freescale com ATA ATAPI 4 AT Attachment with Packet...

Страница 18: ...ata_dma1 MBAR 0x3A10 32 ATA multiword DMA timing 2 ata_dma2 MBAR 0x3A14 32 ATA ultra DMA timing 1 ata_udma1 MBAR 0x3A18 32 ATA ultra DMA timing 2 ata_udma2 MBAR 0x3A1C 32 ATA ultra DMA timing 3 ata_ud...

Страница 19: ...res ata_drive_ftr MBAR 0x3A64 8 write only ATA drive error 8 read only ATA drive sector count ata_drive_sc MBAR 0x3A68 8 R W ATA drive sector number ata_drive_sn MBAR 0x3A6C 8 R W ATA drive cylinder l...

Страница 20: ...emiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or inciden...

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