Freescale Semiconductor HCS08 Series, Справочное руководство

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
238 Freescale Semiconductor
Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is
operating in up/down counting mode so this implies that all active channels within a TPM must be used in
CPWM mode when CPWMS=1.
The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure
coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPMMODH, TPMMODL, TPMCnVH, and TPMCnVL, actually write to buffer registers.
In center-aligned PWM mode, the TPMCnVH:L registers are updated with the value of their write buffer
according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the
TPM counter changes from (TPMMODH:TPMMODL - 1) to (TPMMODH:TPMMODL). If the
TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF.
When TPMCNTH:TPMCNTL=TPMMODH:TPMMODL, the TPM can optionally generate a TOF
interrupt (at the end of this count).
Writing to TPMSC cancels any values written to TPMMODH and/or TPMMODL and resets the
coherency mechanism for the modulo registers. Writing to TPMCnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMCnVH:TPMCnVL.
14.7 Reset Overview
14.7.1 General
The TPM is reset whenever any MCU reset occurs.
14.7.2 Description of Reset Operation
Reset clears the TPMSC register which disables clocks to the TPM and disables timer overflow interrupts
(TOIE=0). CPWMS, MSnB, MSnA, ELSnB, and ELSnA are all cleared which configures all TPM
channels for input-capture operation with the associated pins disconnected from I/O pin logic (so all MCU
pins related to the TPM revert to general purpose I/O pins).
14.8 Interrupts
14.8.1 General
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on each channel’s mode of operation. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register.