Freescale Semiconductor HCS08 Series, Справочное руководство

Страница: 198 / 306

16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
198 Freescale Semiconductor
13.3.5 SPI Data Registers (SPIDH:SPIDL)
The SPI data registers (SPIDH:SPIDL) are both the input and output register for SPI data. A write to these
registers writes to the transmit data buffer, allowing data to be queued and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is transmitted immediately
after the previous transmission has completed.
The SPI transmit buffer empty flag (SPTEF) in the SPIS register indicates when the transmit data buffer
is ready to accept new data. SPIS must be read when SPTEF is set before writing to the SPI data registers,
or the write will be ignored.
5
SPTEF
SPI Transmit Buffer Empty Flag — This bit is set when the transmit data buffer is empty. It is cleared by reading
SPIS with SPTEF set, followed by writing a data value to the transmit buffer at SPIDH:SPIDL. SPIS must be read
with SPTEF = 1 before writing data to SPIDH:SPIDL or the SPIDH:SPIDL write will be ignored. SPTEF is
automatically set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI,
data written to SPIDH:SPIDL is transferred to the shifter almost immediately so SPTEF is set within two bus
cycles allowing a second data to be queued into the transmit buffer. After completion of the transfer of the data
in the shift register, the queued data from the transmit buffer will automatically move to the shifter and SPTEF will
be set to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit buffer,
SPTEF simply remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
4
MODF
Master Mode Fault Flag — MODF is set if the SPI is configured as a master and the slave select input goes low,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading
MODF while it is 1, then writing to SPI control register 1 (SPIC1).
0 No mode fault error
1 Mode fault error detected
7 6 5 4 3 2 1 0
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0
Figure 13-9. SPI Data Register High (SPIDH)
7 6 5 4 3 2 1 0
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 0 0 0 0 0 0 0 0
Figure 13-10. SPI Data Register Low (SPIDL)
Table 13-8. SPIS Register Field Descriptions
Field Description