Freescale Semiconductor HCS08 Series, Справочное руководство

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 229
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
In BDM mode, writing any value to TPMSC, TPMCNTH or TPMCNTL registers resets the read
coherency mechanism of the TPMCNTH:L registers, regardless of the data involved in the write.
14.5.3 TPM Counter Modulo Registers (TPMMODH:TPMMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMMODH or TPMMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPMMODH or TPMMODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the
TPM counter changes from (TPMMODH:TPMMODL - 1) to (TPMMODH:TPMMODL). If the
TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF
The latching mechanism may be manually reset by writing to the TPMSC address (whether BDM is active
or not).
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMSC register) such
that the buffer latches remain in the state they were in when the BDM became active, even if one or both
halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses
the buffer latches and directly writes to the modulo register while BDM is active.
7 6 5 4 3 2 1 0
R Bit 7 6 5 4 3 2 1 Bit 0
W Any write to TPMCNTL clears the 16-bit counter
Reset 0 0 0 0 0 0 0 0
Figure 14-9. TPM Counter Register Low (TPMCNTL)
7 6 5 4 3 2 1 0
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 0 0 0 0 0 0 0 0
Figure 14-10. TPM Counter Modulo Register High (TPMMODH)