Freescale Semiconductor HCS08 Series, Справочное руководство

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Multi-Purpose Clock Generator (S08MCGV1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 121
9.3.2 MCG Control Register 2 (MCGC2)
7 6 5 4 3 2 1 0
R
BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
W
Reset: 0 1 0 0 0 0 0 0
Figure 9-4. MCG Control Register 2 (MCGC2)
Table 9-2. MCG Control Register 2 Field Descriptions
Field Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the
MCGC1 register. This controls the bus frequency.
00
Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
5
RANGE
Frequency Range Select — Selects the frequency range for the external oscillator or external clock source.
1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external
clock source)
0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external
clock source)
4
HGO
High Gain Oscillator Select — Controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
3
LP
Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes.
1 FLL (or PLL) is disabled in bypass modes (lower power)
.
0 FLL (or PLL) is not disabled in bypass modes.
2
EREFS
External Reference Select — Selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
1
ERCLKEN
External Reference Enable — Enables the external reference clock for use as MCGERCLK.
1 MCGERCLK active
0 MCGERCLK inactive
0
EREFSTEN
External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when
the MCG enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or
BLPE mode before entering stop
0 External reference clock is disabled in stop