Freescale Semiconductor CMB2103, Руководство пользователя

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MMCCMB2103UM/D
User’s Manual
55
Logic Analyzer Connectors (J14, J15, J16)
Figure 4-9 Logic Analyzer Connector J15 (A) Pin Assignments
J15
NC 1
• •
38 NC
NC 2
• •
37 NC
CLKOUT 3
• •
36 RW_b
CS_b[1] 4
• •
35 ADDR[15]
CS_b[2] 5
• •
34 ADDR[14]
CS_b[3] 6
• •
33 ADDR[13]
CS_b[4] 7
• •
32 ADDR[12]
NC 8
• •
31 ADDR[11]
NC 9
• •
30 ADDR[10]
NC 10
• •
29 ADDR[9]
NC 11
• •
28 ADDR[8]
NC 12
• •
27 ADDR[7]
ADDR[22] 13
• •
26 ADDR[6]
ADDR[21] 14
• •
25 ADDR[5]
ADDR[20] 15
• •
24 ADDR[4]
ADDR[19] 16
• •
23 ADDR[3]
ADDR[18] 17
• •
22 ADDR[2]
ADDR[17] 18
• •
21 ADDR[1]
ADDR[16] 19
• •
20 GND
Table 4-8 Logic Analyzer Connector J15 (A) Signal Descriptions
Pin Mnemonic Signal
1, 2, 8 — 12, 37,
38
NC No connection
3 CLKOUT CLOCK OUTPUT — An external, low-frequency clock source from the
processor.
4 — 7 CS_b[1] — CS_b[4] CHIP SELECTS (lines 1—4) — Active-low output lines that provide chip selects
to external devices.
13 — 19, 21 —
35
ADDR[22] —
ADDR[1]
(not in exact order)
ADDRESS BUS (lines 22—1) – Output lines for addressing external devices.
These lines change state only during external-memory accesses.
20 GND GROUND
36 RW_b READ/WRITE ENABLE – Active-low signal indicating that the current bus
access is a write access. Otherwise, the current bus access is a read access.
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