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MMCCMB2103UM/D

User’s Manual

45

MAPI Connectors (P1/J1, P2/J2, P3/J3, P4/J4)

Table 4-3  MAPI Connector P3/J3 Signal Descriptions

Pin

Mnemonic

Signal

100, 99, 60, 59, 

VDD3V

+3.3-volt power

98, 96, 94, 92, 
90, 89, 78, 72, 

70, 66, 64, 62, 58 

— 56, 54 — 50, 

48 — 44, 42 — 

38, 36 — 32, 30 

— 26, 22, 20

PTJ3[x]

Pass Through.

97, 95, 91, 81, 
68, 65, 63, 61, 

55, 49, 43, 31, 25

GND

GROUND

93

EXTAL

EXTERNAL CLOCK — Off-board clock signal.

88, 86

TSIZ[1], TSIZ[0]

TRANSFER SIZE (lines 1, 0) — Signals that indicate the size of an external bus 
transfer.

87

TRST_b

TEST RESET – Active-low input signal to the Schmitt trigger, asynchronously 
initializing the test controller.

85

TCLK

TEST CLOCK – Input signal that synchronizes the JTAG test logic. The TCK pin 
has an internal pullup resistor.

84

DBEV_b

DEBUG EVENT – Open-drain, active-low debug signal. If an input signal from 
an external command controller, causes the processor to enter debug mode. If 
an output signal, acknowledges that the MCU is in debug mode.

83

TMS

TEST MODE SELECT – Input signal that sequences the JTAG test controller's 
state machine, sampled on the rising edge of the TCK signal. The TMS pin has 
an internal pullup resistor.

82

TDI

TEST DATA INPUT – Serial input signal for JTAG test instructions and data, 
sampled on the rising edge of the TCK signal. The TDI pin has an internal 
pullup resistor.

80

TDO

TEST DATA OUTPUT – Serial output signal for JTAG test instructions and data. 
Tri-stateable and actively driven in the Shift-IR and Shift-DR controller states, 
this signal changes on the falling edge of the TCK signal.

79

RSTOUT_b

RESET OUT – Active-low output signal, controlled by the processor, that resets 
external components. Activation of any internal reset sources asserts this line.

77

RESET_b

RESET IN – Active-low input signal that starts a system reset: a reset of the 
processor and most peripherals. This signal does not affect the debug module 
(which the system provides via the TRST* line).

76, 37

IDVDD

IDENTIFICATION POWER — Special 3-volt power signal, from an external 
source, for the identification code (MID) signals.

75

SHS

SHOW CYCLE STROBE — Output signal indicating that address and data are 
valid.

74

VDD5V

+5-volt power.

73, 71, 69, 67

PSTAT[3] — 

PSTAT[0]

PROCESSOR STATUS (lines 3—0) — Output signals that provide external 
status indications for the resident MCU.

37

IDVDD

MID (identification code) lines 9—4 — Signals that identify the host processor 
board.

 

   

  

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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Содержание CMB2103

Страница 1: ...product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and...

Страница 2: ...boards are subject to damage from electrostatic discharge ESD To prevent such damage you must use static safe work surfaces and grounding straps as defined in ANSI EOS ESD S6 1 and ANSI EOS ESD S4 1 A...

Страница 3: ...eader W6 19 2 1 6 Setting the RS232 Header W7 19 2 1 7 Setting the Firmware Select Switch S2 20 2 1 8 Setting the Configuration Switches S3 S4 21 2 2 Making Computer System Connections 22 2 3 Performi...

Страница 4: ...3 OnCE Connector J6 53 4 4 Logic Analyzer Connectors J14 J15 J16 54 4 5 Communication Connectors J52 J58 J60 J61 57 Section 5 PRU Board 5 1 PRUB Layout 59 5 2 Connecting the PRUB 60 5 3 Connection Po...

Страница 5: ...44 4 4 MAPI Connector P4 J4 Pin Assignments 47 4 5 ETK Connector J5 Pin 1 to 68 Assignments 49 4 6 ETK Connector J5 Pin 69 to 160 Assignments 50 4 7 OnCE Connector J6 Pin Assignments 53 4 8 Logic Anal...

Страница 6: ...MMCCMM2103UM D User s Manual 6 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 7: ...l Descriptions 43 4 3 MAPI Connector P3 J3 Signal Descriptions 45 4 4 MAPI Connector P4 J4 Signal Descriptions 48 4 5 ETK Connector J5 Signal Descriptions 51 4 6 OnCE Connector J6 Signal Descriptions...

Страница 8: ...MMCCMB2103UM D User s Manual 8 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 9: ...SysDS loader lets you download your code into the CMB2103 s SRAM for execution or FLASH memory for execution or for storage in non volatile memory The CMB2103 will combine easily with other optional d...

Страница 10: ...microprocessor 16 megabytes of RAM 50 megabytes of free hard disk space an SVGA color monitor and an RS232 serial communications port To use the Picobug debug monitor you also need Hyperterminal or a...

Страница 11: ...tor J58 is the connector for communications in the CAN automotive electronics protocol Connectors J60 and J61 are the RS232 serial connectors ports 2 and 1 respectively Switch S1 is the reset switch S...

Страница 12: ...CMB2103 fuse The resident MCU at location U8 is an MMC2103 device in a special 160 pin PQFP package Table 1 1 lists CMB2103 specifications NOTE The factory ships separate rubber feet with your CMB210...

Страница 13: ...ponent Configuration Settings Component Position Effect MMIO Chip Select Header W1 FLASH Chip Select Header W2 FSRAM Chip Select Header W3 or ETK Chip Select Header W4 Configures chip select 1 Factory...

Страница 14: ...ppropriate for MAPI ring communication via a platform board Reset Switch S1 Push to reset all board components Firmware Select Switch S2 Runs built in selftest which can detect board level system prob...

Страница 15: ...res external boot with 32 bit port size Another of many plausible configurations Specifies 25pf output drive strength internal boot with 32 bit port size provided S4 configures master mode and RS232 s...

Страница 16: ...7 and 8 NOTE Each chip select header W1 through W4 must specify a different chip select Do not install multiple jumpers in any of these headers Configuration Switch S4 Enables internal FLASH and spec...

Страница 17: ...tiple jumpers in any of these headers 2 1 3 Setting the FSRAM Chip Select Header W3 Jumper header W3 specifies the FSRAM chip select The diagram below shows the factory configuration the jumper betwee...

Страница 18: ...t 1 2 or 3 for the ETK connector by repositioning the W4 jumper respectively to pins 1 and 2 3 and 4 or 5 and 6 NOTES 1 Each chip select header W1 through W4 must specify a different chip select Do no...

Страница 19: ...sitioning the W6 jumpers between pins 3 and 5 and between pins 4 and 6 2 1 6 Setting the RS232 Header W7 Jumper header W7 activates or deactivates the RS232 I O ports connectors J60 and J61 The diagra...

Страница 20: ...ot matter To specify a different firmware module reset the S2 subswitches per Table 2 2 NOTE User software can read the positions of all four S2 subswitches Table 2 2 S2 Subswitch Settings Firmware Mo...

Страница 21: ...ulation mode For a different configuration reset the S3 and S4 subswitches per Table 2 3 Table 2 3 S3 S4 Subswitch Settings Subswitch ON Configures OFF Configures S3 1 25pf output drive strength recom...

Страница 22: ...ncludes pin assignments and cable descriptions for the logic analyzer connectors 6 Optional You may use ETAS ETK communication with your emulator To do so connect an appropriate cable between CMB2103...

Страница 23: ...out during the test according to the sequence of Table 2 4 6 Then individual LEDs light several times in the sequence DS5 DS4 DS3 and DS2 7 When all four LEDs go out the CMB2103 has passed the selfte...

Страница 24: ...chip select 4 The advantage of this configuration is that the 2 megabytes of CMB SRAM can operate with just one wait state The disadvantage of this configuration is that it allows access to just 4 meg...

Страница 25: ...0_0000 0x807F_FFFF MMIO and MPFB1200 peripherals 1 megabyte CS3 0x8070_0000 0x8070_00FF MPFB1200 peripherals 128 bytes 0x8070_0100 0x8070_7002 unused 0x8070_7003 MMIO read byte reads S2 subswitch sett...

Страница 26: ...SH Sector Boundaries Sector Block Range 0 0x8000_0000 0x8000_7FFF 1 0x8000_8000 0x8000_BFFF 2 0x8000_C000 0x8000_FFFF 3 0x8001_0000 0x8001_FFFF 4 0x8002_0000 0x8003_FFFF 5 0x8004_0000 0x8005_FFFF 6 0x...

Страница 27: ...r and ground locations Note that separate columns or rows of each prototyping area are 3 3 volt sources 5 volt sources and ground connections The two eyelet areas offer convenient connection to key si...

Страница 28: ...n 4 includes signal descriptions for connectors P1 and P3 P3 Pin Signal Signal P3 Pin 60 VDD3V AGND 11 18 AN 48 14 AN 2 AN 3 16 10 AN 0 AN 1 12 6 AN 55 AN 56 8 2 AN 53 AN 54 4 Freescale Semiconductor...

Страница 29: ...nal emulation program If you use a different terminal emulation program you must make corresponding changes in the commands and menu selections of these instructions and in the instructions of paragra...

Страница 30: ...dress2 values displays memory contents between the addresses With optional address1 value displays contents of 16 memory bytes With no address value defaults to the last address viewed The optional si...

Страница 31: ...es of all CPU registers rm name value Register Modify Assigns the value parameter value to the name CPU register t Trace Step Single steps one instruction identical to the s command s Step Trace Singl...

Страница 32: ...box to specify the appropriate S record file then click on the Open button As soon as the download is complete this may take several minutes the Picobug prompt reappears 7 To see the new contents of...

Страница 33: ...firming that the system has removed the breakpoints 12 To see the list of breakpoints again once more enter the Breakpoint br command without any address value As there are no longer any breakpoints t...

Страница 34: ...verifying displaying erasing or blank checking the software may download algorithm file programmer2103 rec before carrying out the action If the software cannot find the algorithm file an appropriate...

Страница 35: ...OK button This returns you to the main screen entering the pathname in the File name field If your only action for this Loader session will be uploading FLASH contents you may leave the File name fiel...

Страница 36: ...ng A likely such problem is that the chip select base address does not correspond to the configured chip select Correct the problem then click again on the Download button 10 To upload FLASH memory co...

Страница 37: ...download file 12 To view the contents of Flash memory click on the Display button This brings up the Display Flash Ram display Figure 3 3 Figure 3 3 Display Flash Ram Display The Address field shows...

Страница 38: ...5 To verify that a FLASH sector is blank click on the Blank Check button This brings up a dialog box that asks for a sector number Enter the number of the sector to be blank checked then click on the...

Страница 39: ...nectors are the CMB2103 MAPI connectors Connectors J1 through J4 on the bottom of the CMB2103 have the same pin assignments The diagram below shows the orientation of the CMB2103 MAPI connectors Figur...

Страница 40: ...IRQ_b 0 62 61 PTJ1 61 VDD3V 60 59 VDD3V GND 58 57 TXD 1 PTJ1 56 56 55 RXD 1 PTJ1 54 54 53 TXD 2 GND 52 51 RXD 2 PTJ1 50 50 49 PCS 0 SCK 48 47 PCS 1 GND 46 45 PCS 2 MOSI 44 43 PCS 3 MISO 42 41 GND GND...

Страница 41: ...CS 0 PCS 3 PERIPHERAL CHIP SELECTS lines 0 3 Chip select lines for peripheral devices 48 SCK SERIAL CLOCK If SPI is enabled the serial clock signal If SPI is disabled a general purpose port E I O sign...

Страница 42: ...59 PTJ2 59 PTJ2 58 58 57 PTJ2 57 PTJ2 56 56 55 PTJ2 55 PTJ2 54 54 53 PTJ2 53 PTJ2 52 52 51 PTJ2 51 PTJ2 50 50 49 PTJ2 49 PTJ2 48 48 47 PTJ2 47 GND 46 45 VDD5V VDD3V 44 43 GND PTJ2 42 42 41 PTJ2 41 PTJ...

Страница 43: ...nalog digital converter 96 MAPIVREFL MAPI VOLTAGE REFERENCE LOW Low reference for voltage supplied via the MAPI ring 94 MAPOIVREFH MAPI VOLTAGE REFERENCE HIGH High reference for voltage supplied via t...

Страница 44: ...ND VDD3V 60 59 VDD3V PTJ3 58 58 57 PTJ3 57 PTJ3 56 56 55 GND PTJ3 54 54 53 PTJ3 53 PTJ3 52 52 51 PTJ3 51 PTJ3 50 50 49 GND PTJ3 48 48 47 PTJ3 47 PTJ3 46 46 45 PTJ3 45 PTJ3 44 44 43 GND PTJ3 42 42 41 P...

Страница 45: ...ATA INPUT Serial input signal for JTAG test instructions and data sampled on the rising edge of the TCK signal The TDI pin has an internal pullup resistor 80 TDO TEST DATA OUTPUT Serial output signal...

Страница 46: ...gital converter 18 16 14 12 10 8 6 4 2 AN 48 AN 3 AN 0 AN 56 AN 53 ANALOG IN lines 48 3 0 55 53 Analog input channels for the analog digital converter Table 4 3 MAPI Connector P3 J3 Signal Description...

Страница 47: ...ADDR 16 60 59 ADDR 17 GND 58 57 GND ADDR 14 56 55 ADDR 15 ADDR 12 54 53 ADDR 13 ADDR 10 52 51 ADDR 11 ADDR 8 50 49 ADDR 9 ADDR 6 48 47 ADDR 7 ADDR 4 46 45 ADDR 5 ADDR 2 44 43 ADDR 3 PTJ4 42 42 41 ADDR...

Страница 48: ...23 D16 for enable byte 1 D15 D8 for enable byte 2 D7 D0 for enable byte 3 81 RW_b READ WRITE ENABLE Active low signal indicating that the current bus access is a write access Otherwise the current bus...

Страница 49: ...6 11 VDD5V NC 9 12 GND DATA 0 10 15 DATA 3 DATA 1 13 16 DATA 4 DATA 2 14 19 DATA 6 DATA 5 17 20 DATA 7 GND 18 23 DATA 10 DATA 8 21 24 DATA 11 DATA 9 22 27 GND DATA 12 25 28 DATA 14 DATA 13 26 31 DATA...

Страница 50: ...103 NC GND 101 104 GND GND 102 107 GND GND 105 108 NC SHS_b 106 111 NC RESET_b 109 112 GND GND 110 115 GND RSTOUT_b 113 116 CLKOUT VDD3V 114 119 GND GND 117 120 NC NC 118 123 GND NC 121 124 GND GND 1...

Страница 51: ...78 SGCSM_b ETK CHIP SELECT General purpose chip select for program data to the dual port RAM 80 RW_b READ WRITE ENABLE Active low signal indicating that the current bus access is a write access Other...

Страница 52: ...rce from the processor 125 SGTCK ETK TEST CLOCK Input signal that synchronizes the JTAG test logic 126 SGTMS ETK TEST MODE SELECT Input signal that sequences the JTAG test controller s state machine s...

Страница 53: ...ontroller 5 TCK TEST CLOCK Serial clock input line to the OnCE control block 7 13 NC No connection 8 Cut to be connector key 9 RESET_b RESET IN Active low input line to the OnCE controller signalling...

Страница 54: ...A 10 DATA 25 10 29 DATA 9 DATA 24 11 28 DATA 8 DATA 23 12 27 DATA 7 DATA 22 13 26 DATA 6 DATA 21 14 25 DATA 5 DATA 20 15 24 DATA 4 DATA 19 16 23 DATA 3 DATA 18 17 22 DATA 2 DATA 17 18 21 DATA 1 DATA 1...

Страница 55: ...nal Descriptions Pin Mnemonic Signal 1 2 8 12 37 38 NC No connection 3 CLKOUT CLOCK OUTPUT An external low frequency clock source from the processor 4 7 CS_b 1 CS_b 4 CHIP SELECTS lines 1 4 Active low...

Страница 56: ...nector pins that may be used to connect other system signals to a logic analyzer 8 9 TSIZ 1 TSIZ 0 TRANSFER SIZE lines 1 0 Signals that indicate the size of an external transfer 12 15 P_PSTAT 3 P_PSTA...

Страница 57: ...ve low signal indicating that the current memory cycle is addressing on board devices 33 IRQ_b 0 INTERRUPT REQUEST Active low output indicating that the processor core is servicing an internal interru...

Страница 58: ...ector J58 Table 4 11 lists the pin assignments and signal directions for these connectors Table 4 11 Communication Connector J60 J61 Pin Assignments Pin Signal Signal Direction 1 4 6 9 No connection 2...

Страница 59: ...a custom connector to connect PRUB port eyelets directly to a target system in the fashion of a 40 pin parallel port 5 1 PRUB Layout Figure 5 1 shows the layout of the PRUB Connectors P1 through P4 o...

Страница 60: ...B1200 to line up vertically the right triangle markings by MAPI connectors P1 and P2 of the boards 4 Press the MPFB1200 down onto the PRUB so that MPFB1200 connectors J1 through J4 on the bottom of th...

Страница 61: ...ists have not tested and do not recommend any other board combination Connect your power cable to the MPFB1200 not to the CMB2103 Connect other cables to the appropriate board For example Connect an R...

Страница 62: ...P1 J1 and P2 J2 are pass through connectors just as are the MAPI connectors of other boards Figure 5 3 shows in bold type the J3 pins that have different assignments than their P3 counterparts Similar...

Страница 63: ...2 62 61 GND VDD3V 60 59 VDD3V PTJ3 58 58 57 PTJ3 57 PTJ3 56 56 55 GND PTJ3 54 54 53 PTJ3 53 PTJ3 52 52 51 PTJ3 51 PTJ3 50 50 49 GND PTJ3 48 48 47 PTJ3 47 PTJ3 46 46 45 PTJ3 45 PTJ3 44 44 43 GND PTJ3 4...

Страница 64: ...50 49 ADDR 9 ADDR 6 48 47 ADDR 7 ADDR 4 46 45 ADDR 5 ADDR 2 44 43 ADDR 3 PTJ4 42 42 41 ADDR 1 GND 40 39 GND DATA 30 PA6 J4 38 37 DATA 31 PA7 J4 DATA 28 PA4 J4 36 35 DATA 29 PA5 J4 DATA 26 PA2 J4 34 33...

Страница 65: ...CSE0_MAPI signal Each of these signals has one of four coded values according to the assertion levels of two lines You may connect to the J7 or J19 eyelets to read these assertion levels Table 5 1 Por...

Страница 66: ...MMCCMB2103UM D User s Manual 66 PRU Board Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Страница 67: ...or J14 54 logic analyzer connector J15 55 logic analyzer connector J16 56 MAPI connectors P1 J1 P4 J4 41 43 45 48 OnCE connector J6 53 D debugging embedded code 29 34 E ETK chip select header W4 18 ET...

Страница 68: ...nfiguration switches S3 S4 21 ETK chip select header W4 18 firmware select switch S2 20 FLASH chip select header W2 17 FLASH data bus access header W1 16 FSRAM chip select header W3 17 MMIO chip selec...

Страница 69: ...ual 69 Revision History Revision Number Date Author Summary of Changes Original July 2000 MTC DDOC Original document Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This...

Страница 70: ...y Center Design Documentation team Technical writing illustration and production editing performed with Adobe Framemaker running on multiple platforms Printed by Ken Cook Inc in Milwaukee Wisconsin Fr...

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