Force Computers PENT/CPCI-721, Руководство по установке

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Maps and Registers PENT/CPCI-720/2/3 Registers
PENT/CPCI-721 6 - 13
Watchdog Control and Retrigger Register
The Watchdog Control and Retrigger register specifies watchdog
related settings. The watchdog time-out value is fixed to approximately
1.5 s.
Table 22: Watchdog Control Register
Address: 010A
16
Bit Value Description Access Settings
0 WDOG_ON Controls whether the
watchdog timer is enabled
or disabled. r/w = 0
Watchdog timer
is enabled.
= 1
(default)
Watchdog timer
is disabled.
1 WDOG_RESET
/NMI Controls whether an NMI
or a reset is caused when
the watchdog timer is not
retriggered within the time-
out period. r/w = 0
An NMI is
caused.
=1 (default)
A reset is caused.
For information
whether the reset
is local or global,
see the
RESET_BUS
(r/w) bit in the
PCI Bus Control
Register.
2 WDOG_HW/
SW Controls whether the
watchdog timer has to be
retriggered by software or
by hardware. r/w = 0
Software control
mode: The
watchdog timer
has to be retrig-
gered by soft-
ware using the
WDOG_RETR
(w) bit in the
Watchdog
Retrigger Regis-
ter.
=
1 (default)
Hardware con-
trol mode: The
PENT/CPCI-721
retriggers the
watchdog timer.
3 Reserved r Undefined