Instruction List (12)
S1C63000 Core CPU
Opcode
LDB
LDB
LDB
LDB
LDB
LDB
LDB
ADD
CMP
INC
DEC
PUSH
POP
Operand
%BA,imm8
%BA,[%X]+
%BA,[%Y]+
%XL,%BA
%XL,imm8
%XH,%BA
%YL,%BA
%YL,imm8
%YH,%BA
%EXT,%BA
%EXT,imm8
%SP1,%BA
%SP2,%BA
[%X]+,%BA
[%X]+,imm8
[%Y]+,%BA
%X,%BA
%X,sign8
%Y,%BA
%Y,sign8
%X,imm8
%Y,imm8
%SP1
%SP2
%SP1
%SP2
%A
%B
%F
%X
%Y
%A
%B
%F
%X
%Y
Basic function
BA
←
imm8
A
←
[X], B
←
[X+1], X
←
X+2
A
←
[Y], B
←
[Y+1], Y
←
Y+2
XL
←
BA
XL
←
imm8
XH
←
BA
YL
←
BA
YL
←
imm8
YH
←
BA
EXT
←
BA
EXT
←
imm8
SP1
←
BA
SP2
←
BA
[X]
←
A, [X+1]
←
B, X
←
X+2
[X]
←
i3~0, [X+1]
←
i7~4, X
←
X+2
[Y]
←
A, [Y+1]
←
B, Y
←
Y+2
X
←
X+BA
X
←
X+sign8 (sign8=-128~127)
Y
←
Y+BA
Y
←
Y+sign8 (sign8=-128~127)
X-imm8 (imm8=0~255)
Y-imm8 (imm8=0~255)
SP1
←
SP1+1
SP2
←
SP2+1
SP1
←
SP1-1
SP2
←
SP2-1
[SP2-1]
←
A, SP2
←
SP2-1
[SP2-1]
←
B, SP2
←
SP2-1
[SP2-1]
←
F, SP2
←
SP2-1
([(SP1-1)
∗
4+3]~[(SP1-1)
∗
4])
←
X, SP1
←
SP1-1
([(SP1-1)
∗
4+3]~[(SP1-1)
∗
4])
←
Y, SP1
←
SP1-1
A
←
[SP2], SP2
←
SP2+1
B
←
[SP2], SP2
←
SP2+1
F
←
[SP2], SP2
←
SP2+1
X
←
([SP1
∗
4+3]~[SP1
∗
4]), SP1
←
SP1+1
Y
←
([SP1
∗
4+3]~[SP1
∗
4]), SP1
←
SP1+1
Extended function
(when "LDB %EXT, imm8" is executed)
–
–
–
–
X
←
imm16 (imm8 set in EXT is used as high-order 8 bits)
–
–
Y
←
imm16 (imm8 set in EXT is used as high-order 8 bits)
–
–
–
–
–
–
–
–
–
X
←
X+imm16 (imm8 set in EXT is used as high-order 8 bits)
–
Y
←
Y+imm16 (imm8 set in EXT is used as high-order 8 bits)
X-imm16 (imm8 set in EXT is used as high-order 8 bits)
Y-imm16 (imm8 set in EXT is used as high-order 8 bits)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Symbol
●
,@h
–
–
–
●
,@l
–
–
●
,@l
–
–
●
,@l,@h
@rh,@xh
–
–
–
●
,@l,@h
–
–
●
,@l
–
●
,@l
●
,@l
●
,@l
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Clk
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↔
↔
–
–
–
–
–
–
–
–
–
–
–
↔
–
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↔
↔
↔
↔
↔
↔
↔
↔
↔
–
–
–
–
–
–
–
–
↔
–
–
E
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↔
0
0
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↔
–
–
Mnemonic
Classification
8/16-bit
transfer and
operation
Stack
operation
Flags
Remarks
Содержание S5U1C63000A
Страница 1: ...MF910 06 CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63 Family Assembler Package S5U1C63000A Manual ...
Страница 4: ......
Страница 14: ......
Страница 304: ......
Страница 305: ...S1C63 Family Assembler Package Quick Reference ...