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Epson Research and Development
Vancouver Design Center
S1D13700
S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01
Issue Date: 2005/07/15
Revision 1.0
A.4 Bus Disable
Switch SW1 is used to disable the bus to the Epson Mobile Graphics Engine evaluation
board. When the bus is disabled, the red LED (D2) turns “ON”. For normal operations, the
bus should be enabled, with SW1 positioned towards the clock X1 location.
Note
On some systems, the Bus Disable function must be “ON” when the PC Card Extender
Board/Evaluation board combination is first plugged into the PC Card host. Once the
OS has detected the PC Card, the Bus Disable function can be turned “OFF”.
A.5 16-Bit PC Card Mode
To select 16-bit PC Card mode, switch SW2 must be positioned toward the clock X1
location. The S1D13700 is a 16-bit device and the drivers for the PC Card have been
configured for 16-bit devices only. Therefore, 8-bit byte steering logic is not needed from
the PC Card and should be placed in the 16-bit position.
A.6 Generic #1 / #2 Bus
Switch SW3 selects the control signals between Generic #1 or Generic #2 bus. The
S5U13700B00C Evaluation Board does not require the setting of this switch and it should
be positioned towards the clock X1 location.
A.7 Epson Evaluation Boards
The extender card provides a header to interface to Epson Mobile Graphics Engine Evalu-
ation Boards. The header contains all the signals necessary for interfacing to the PC Card
bus. The signals on the bus have been level shifted from 5V to 3.3V.
Vcc from the PC Card Bus is provided on the header, but considerations to the current draw
should be noted. The evaluation board needs to supply it’s own Vcc if the current draw is
greater than what the PC Card bus can provide.
A.8 Epson Evaluation Board Header Pin Mapping
The CPU interface uses two female connectors (P1 and P2) which provide all the signals
and power connections needed for direct PC Card. Generic #1 and Generic#2 bus control
signals have been decoded and are selectable using SW2.
Refer to the schematics for the pinout of P1 and P2.
