Epson Research and Development
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Vancouver Design Center
S5U13513P00C100 Evaluation Board User Manual
S1D13513
Issue Date: 2010/09/06
X78A-G-003-01
Revision 1.1
3 Installation and Configuration
The S5U13513P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm
resistors which allow it to be used with a variety of different configurations.
3.1 Configuration DIP Switch
The S1D13513 has configuration inputs (CNF[8:0]) which are read on the rising edge of
RESET#. A 10-position DIP switch (SW1) is used to configure the S1D13513 for multiple
Host Bus Interfaces. The following figure shows the location of DIP switch SW1 on the
S5U13513P00C100.
Figure 3-1: Configuration DIP Switch (SW1) Location
All S1D13513 configuration inputs (CNF[8:0]) are fully configurable using DIP switch
SW1 as described below.
Table 3-1: Summary of Power-On/Reset Options
SDU13513B00C
SW1-[10:1] Config
S1D13513
CNF[8:0] Config
Power-On/Reset State
1 (ON)
0 (OFF)
SW1-[10]
-
Not used
SW1-[9:8]
CNF[8:7]
00b
CLKI3 is the PLL1 clock source
01b
BUSCLK is the PLL1 clock source
10b
OSC1 is the PLL1 clock source
11b
OSC2 is the PLL1 clock source
SW1-[6]
CNF5
Indirect access
Direct access
SW1-[7]
CNF6
See Table 3-2: “CNF[4:0] Setting
See Table 3-3: “CNF[4:0] Setting for
CNF[6] = 0b”
SW1-[5:1]
CNF[4:0]
00000b
Parallel Direct 80 Type 2: 1CS#
(see Table 3-2: “CNF[4:0] Setting for CNF[6] = 1b” )
= Required settings when using S5U13U00P00C100 USB Adapter board (SW1-[9:1] = 101000000b)
DIP SWITCH - SW1